MOSFET Carrier FlowN-channel · Vth = +1.0 V · body tied to source

How a MOSFET turns on, step by step

1. Off: with no gate voltage the body’s majority carriers (holes in an NMOS) sit right under the oxide. The source and drain are separated by two back-to-back PN junctions, so nothing flows.
2. Depletion: a small positive gate voltage pushes the holes away. Fixed, charged dopant ions are left behind. They cannot move, so there is still no current.
3. Inversion: above the threshold voltage Vth, the gate pulls in enough electrons to form a thin n-type layer under the oxide: the channel. It now connects source and drain.
4. Linear (triode): a small VDS makes electrons drift through the channel. The device behaves like a resistor whose value the gate sets.
5. Saturation: once VDS ≥ VGS − Vth, the channel pinches off at the drain end. Extra VDS mostly drops across the drain depletion region, so the current levels off.

Conditions with your current settings:

Why the current stops growing in saturation

The gate-to-channel voltage at the drain end is VGS − VDS. When that falls to Vth, the drain end of the channel can hold no more carriers: it pinches off. Carriers that reach the pinch-off point are swept across the strong field of the drain depletion region, so the current is set by how many carriers the channel can supply, ½k(VGS − Vth)², not by VDS.

NMOS vs PMOS

Device terms

Source / Drain

Heavily doped regions (n+ or p+) where carriers enter and leave the channel.

Gate

Electrode on top of a thin oxide. Its voltage attracts or repels carriers below it; no DC current flows into it.

Body

The substrate or well the transistor sits in. Usually tied to the source.

Oxide

Thin insulating SiO₂ (or high-k) layer between gate and silicon.

Majority carrier

The carrier the body is doped with: holes in p-type, electrons in n-type.

Depletion region

A zone emptied of mobile carriers, leaving fixed ions.

Fixed ion

An ionised dopant atom locked in the crystal: acceptors are −, donors are +.

Inversion

The surface switches type (p → n for NMOS) because the gate attracted enough minority carriers.

Vth

Threshold voltage: the VGS where inversion starts and a channel forms.

VOV

Overdrive, VGS − Vth: how far above threshold the gate is.

k = μCox·W/L

Transconductance parameter: mobility × oxide capacitance × width/length. Sets how much current the device gives.

Pinch-off

The point where the channel thickness reaches zero at the drain end.

Short-channel effects

CLM (λ)

Channel-length modulation: the pinch-off point moves toward the source as VDS rises, so ID still grows a little in saturation.

DIBL

Drain-induced barrier lowering: in a short channel the drain field lowers the source barrier, so Vth drops as VDS rises.

Velocity saturation

Carriers have a top speed (~10⁷ cm/s). Short channels reach it, so current saturates early and grows only linearly with VGS.

Body effect

Reverse body bias widens depletion and raises Vth. See the Body effect tab.

How a CMOS inverter works

1. The PMOS connects the output to VDD, the NMOS connects it to ground. Both gates share the input.
2. Input low: the NMOS is off and the PMOS is on, so the output is pulled up to VDD (logic 1).
3. Input high: the PMOS is off and the NMOS is on, so the output is pulled down to 0 V (logic 0).
4. Only one transistor is on in each steady state, so almost no current flows. Current flows only briefly while switching, when both are partly on.

The five regions of the transfer curve

The switching point VM is where Vout = VDD/2. It sits where the NMOS and PMOS are equally strong. Holes are slower than electrons, so with equal widths the PMOS loses and VM moves below VDD/2. Making the PMOS about 2.5× wider balances them and gives equal noise margins for 0 and 1.

Where the power goes

Static power is almost zero. Dynamic power is spent charging and discharging the load capacitance each time the output switches: P = α·C·VDD²·f. That is why lowering VDD (see DVFS in the Power tab) saves so much energy.

Inverter terms

VTC

Voltage transfer curve: Vout plotted against Vin.

VM

Switching threshold: the input where Vout = Vin = VDD/2.

Noise margin

How much noise an input can carry and still be read correctly (NML for logic 0, NMH for logic 1).

Pull-up / pull-down

The PMOS pulls the output up to VDD; the NMOS pulls it down to ground.

Through current

Also called short-circuit current: flows from VDD to ground only while both transistors are partly on.

Wp/Wn

Width ratio. A wider PMOS compensates for slower holes.

kn, kp

Strength of each transistor: μCox·W/L.

Rail-to-rail

The output swings all the way from 0 V to VDD.

Gain region

Region C, where both devices are saturated and a small Vin change gives a large Vout change.

Dynamic power

α·C·VDD²·f: energy spent charging the output capacitance every switching event.

Channel effects here

Short L

Both transistors get stronger, so the through-current peak grows.

CLM / DIBL

The saturated current keeps rising with VDS, so the curve is less steep (lower gain) in region C.

No body effect

Each source is tied to its body (NMOS to ground, PMOS to VDD), so VSB = 0.

What the body effect is

1. Every MOSFET has a fourth terminal, the body (substrate or well). In digital circuits it is tied to ground (NMOS) or VDD (PMOS).
2. If the source rises above the body, the source-body junction is reverse-biased by VSB.
3. That reverse bias widens the depletion layer under the gate, so it holds more fixed charge.
4. The gate must now overcome that extra charge before it can form a channel, so the threshold voltage rises: Vth = Vth0 + γ(√(2φF + VSB) − √2φF).

Right now:

How designers live with it

• In a NAND/NOR stack, put the latest-arriving (critical) input on the transistor closest to the output, so the slow-to-settle middle node is already charged.
• Keep stacks short (2–3 transistors) and size the stacked devices wider.
• Use a transmission gate (NMOS + PMOS) instead of a single pass transistor, so a full 0 and 1 are passed.
• In analog circuits, put the transistor in its own well (or a deep n-well / triple-well process) and tie body to source, which removes the effect.

Terms

Body / bulk

The silicon the transistor is built in: p-substrate for NMOS, n-well for PMOS.

VSB / VBS

Source-to-body voltage (NMOS) or body-to-source voltage (PMOS). Positive means reverse bias.

γ (gamma)

Body-effect coefficient, √(2qεNA)/Cox. Higher doping or thicker oxide gives a bigger γ.

2φF

Surface potential at strong inversion, about 0.6–0.8 V depending on doping.

Stack

Transistors in series. Only the bottom one has its source on the rail.

Node X / Y

The internal node between two stacked transistors. Its voltage is the VSB of the upper device.

Weak 1

An NMOS can only pass up to VDD − Vth(raised): about 1.9 V instead of 3.3 V here.

Transmission gate

NMOS and PMOS in parallel: the PMOS passes the high level the NMOS cannot.

Source follower

Amplifier whose output (source) follows its input (gate) one VGS lower.

gm, gmb

Gate and body transconductance. gmb = η·gm acts against gm in a follower.

η

γ / (2√(2φF + VSB)): body-effect factor, usually 0.1–0.3.

Level shift

The DC drop Vin − Vout of a follower: Vth + VOV.

Two ways to make a lower voltage

With your current settings:

How the output voltage is changed (modulated)

1. LDO: Vout = Vref·(1 + R1/R2). Change the divider ratio or the reference voltage.
2. Buck: Vout ≈ D·Vin. The controller changes the duty cycle D: the PWM comparator keeps the high side on until the ramp crosses the error-amplifier output.
3. PMIC: the processor writes a VSEL code over I²C/SPMI. A DAC turns the code into a new reference, and the regulator’s loop moves the output there at a controlled slew rate.

Why it matters: a processor’s dynamic power is P = α·C·V²·f. Dropping the core from 1.05 V to 0.60 V at idle cuts that power by about 3×, which is the whole point of DVFS.

LDO terms

LDO

Low-dropout linear regulator: works with Vin only slightly above Vout.

Pass device

The large PMOS between input and output that carries the load current.

Error amplifier

Compares the divided output (FB) with Vref and drives the pass-device gate.

Vref

A precise internal reference voltage (0.8 V here), often from a bandgap circuit.

Dropout

Minimum Vin − Vout for regulation. Below it the output just follows Vin.

Load / line regulation

How much Vout changes when the load current / input voltage changes.

PSRR

Power-supply rejection: how well input ripple is kept out of the output.

Load transient

The dip or overshoot of Vout when the load current jumps, before the loop catches up.

Switching and PMIC terms

Buck

Step-down switching converter.

Duty cycle D

Fraction of the period the high-side switch is on.

PWM

Pulse-width modulation: the control method that sets D.

SW node

The switch node between the two transistors; a square wave between Vin and 0 V.

High / low side

The switch to Vin (PMOS here) and the switch to ground (NMOS here).

ΔiL

Inductor ripple current: (Vin − Vout)·D/(f·L).

CCM / DCM

Continuous / discontinuous conduction: whether the inductor current stays above zero.

PMIC

Power-management IC: several regulators, references and control logic in one chip.

Rail

One supply output (e.g. CPU core, I/O, analog).

DVFS

Dynamic voltage and frequency scaling: lower V and f when the load is light.

VSEL

Register that selects the output voltage of a regulator.

Slew rate

Speed of a voltage change, e.g. 10 mV/µs.

How the radar turns distance into a tone

1. The radar sends a chirp: a signal whose frequency rises steadily, e.g. 76 → 77 GHz in 40 µs.
2. The echo comes back a little later, so at every moment it is at a slightly lower frequency than what is being sent.
3. Mixing the echo with the transmit signal leaves the difference: a tone called the beat frequency fb. The farther the target, the longer the delay and the higher the tone: fb = 2·R·S / c.
4. The receiver filter and ADC only pass tones up to the IF bandwidth (20 MHz here). The distance whose tone just reaches that limit is Rmax.

With your current settings:

What “no peak” means

No peak means the radar cannot detect that target with the current chirp settings. The car is still there, but its tone is above the receiver bandwidth, so it is filtered out before the FFT ever sees it. It is not a fault: it is the limit of that chirp design.

Why a larger bandwidth B shortens Rmax

Sweeping more bandwidth in the same time makes the chirp steeper, so every target’s tone is higher and the 20 MHz limit is reached at a shorter distance. Same 60 m car:

This is the basic trade-off: large B gives fine detail (ΔR = c/2B, 3.75 cm at 4 GHz) but a steep chirp gives short reach. Real ADAS radars switch between modes:

Rmax in this demo is only the limit set by the receiver bandwidth. A real radar has a second limit: echo strength falls roughly as 1/R⁴, so a far or small target (a pedestrian instead of a truck) can be too weak to rise above the noise. That limit is not modelled here.

FMCW terms

Chirp

A signal whose frequency rises linearly with time.

B

Chirp bandwidth: how far the frequency sweeps (e.g. 1 GHz).

Tc

Chirp duration: how long one sweep lasts.

S

Slope, S = B/Tc: how fast it sweeps (MHz per µs).

τ

Round-trip delay, τ = 2R/c (400 ns for 60 m).

fb / IF

Beat (intermediate) frequency after the mixer, fb = S·τ. It encodes distance.

IF bandwidth

Highest beat frequency the filter and ADC pass (20 MHz here).

Rmax

Farthest distance whose tone fits in the IF bandwidth: fIF,max·c/(2S).

FFT peak

The FFT finds which tones are present. Each peak is one target; its position gives the distance.

ΔR

Range resolution, c/2B: two targets closer than this merge into one peak.

Doppler

A moving target shifts the echo phase a little from chirp to chirp; that rate gives its speed (fd = 2v/λ).

λ

Wavelength, about 3.9 mm at 77 GHz.

PLL / synthesizer terms

XO / fref

Crystal oscillator: a very stable, low-frequency reference (e.g. 50 MHz).

VCO

Voltage-controlled oscillator: its frequency follows the tuning voltage Vtune.

Varactor

A MOS capacitor whose capacitance changes with voltage (accumulation = high C, depletion = low C). It tunes the VCO.

÷N

Divider: brings the VCO down to fref so it can be compared. Fractional N allows any frequency, not just multiples of fref.

ΣΔ

Sigma-delta modulator: switches the divider between N and N+1 so the average equals the fractional N.

PFD / CP / LF

Phase-frequency detector, charge pump and loop filter: measure the phase error and turn it into a smooth Vtune.

Loop BW

How fast the loop reacts. Wider tracks the chirp better and cleans VCO noise; narrower filters reference and ΣΔ noise.

Phase noise

Random jitter of the carrier phase, in dBc/Hz at an offset frequency. It raises the noise floor around every FFT peak.

×4

Frequency multiplier: 19–20 GHz VCO → 76–81 GHz output (phase noise rises by 20·log4 = 12 dB).

How to read S-parameters

1. Each port of a component is fed from a line with a reference impedance Z0, usually 50 Ω. Power travels in as a wave a and comes back out as a wave b.
2. Sij is the wave leaving port i when only port j is driven: S11 is the reflection at port 1, S21 the transmission from port 1 to port 2.
3. They are complex numbers: the magnitude (usually in dB) says how much comes out, the angle says how much it is delayed.
4. A passive, lossless component keeps the power: |S11|² + |S21|² + … = 1 for each driven port. Whatever is not reflected or passed on is turned into heat or radiated.

With your current settings:

Return loss, VSWR and mismatch

A common target is |S11| below −10 dB across the band: only 10 % of the power is reflected.

TE, TM and TEM

In a TE mode the electric field is purely transverse (Ez = 0) and the magnetic field has a component along the guide. In a TM mode it is the other way round (Hz = 0). A TEM wave has neither Ez nor Hz; it needs two conductors (coax, microstrip, a pair of wires) and has no cutoff. A hollow metal pipe has only one conductor, so it carries only TE and TM modes, and each mode propagates only above its cutoff frequency.

Network terms

Z0

Reference (characteristic) impedance of the ports, 50 Ω here.

Γ = S11

Reflection coefficient: (Z − Z0)/(Z + Z0). 0 means matched, 1 means everything bounces back.

Return loss

−20·log|S11|. Bigger is better.

Insertion loss

−20·log|S21|: how much weaker the signal is after passing through.

VSWR

Ratio of the maximum to the minimum of the standing wave, (1 + |Γ|)/(1 − |Γ|).

Smith chart

A map of Γ. The centre is a perfect match; circles are constant resistance, arcs constant reactance.

λ/4 transformer

A quarter-wave line of Zl = √(Z1·Z2) matches Z1 to Z2.

Component terms

Directional coupler

Four-port that taps a fixed fraction of a wave travelling one way, e.g. to measure the forward power of a PA.

Coupling / isolation

Coupling: input to coupled port. Isolation: input to the port that should get nothing.

Directivity

Isolation minus coupling: how well the coupler tells forward from reflected waves.

Even / odd mode

The two ways a pair of coupled lines can be driven (in phase / opposite). Their impedances Z0e and Z0o set the coupling.

Hybrid

A 3 dB coupler: two equal outputs, 90° (quadrature) or 180° apart.

Balun

BALanced–UNbalanced: turns a single-ended signal into two equal, opposite (differential) signals and back.

Amplitude / phase imbalance

How far the two balun outputs are from equal size and exactly 180° apart.

CMRR

Common-mode rejection: differential output compared with the leftover in-phase part.

Dipole

Two straight wires fed in the middle. Resonant when about half a wavelength long.

Radiation resistance

The part of the antenna's input resistance that stands for power radiated away (73 Ω for a half-wave dipole).

Directivity (dBi)

How much stronger the antenna radiates in its best direction than an ideal isotropic antenna.

E-plane pattern

Radiation versus angle in the plane that contains the dipole; nulls are along the wire.

Low-pass / high-pass

A filter that passes frequencies below / above its cutoff and blocks the rest. A lossless LC filter blocks by reflecting the power back, not by burning it.

Filter order N

Number of L and C elements. Each one adds 20 dB per decade (6 dB per octave) to the slope outside the passband.

Butterworth / Chebyshev

Butterworth is maximally flat in the passband; Chebyshev allows a small ripple (0.5 dB here) in exchange for a steeper edge.

Stepped-impedance filter

A low-pass filter made only of line sections: short, narrow high-Z lines act like series inductors and short, wide low-Z lines like shunt capacitors.

Richards' transformation

A short-circuited stub of length λ/8 at fc has jX = jZs·tan(βl), which behaves like an inductor; an open stub behaves like a capacitor.

Coaxial cavity low-pass

A metal tube with a centre rod: thin rod sections (high Z) act as series L, wide discs (low Z) as shunt C. Air-filled, so very low loss and high power.

Waveguide high-pass

A hollow guide passes nothing below the cutoff of its TE10 mode, fc = c/2a. Below it the field decays as e^(−αz), so the guide itself is the filter.

Band-pass filter

Passes a band around f0 and blocks both sides. Made from resonators tuned to f0 whose couplings set the bandwidth.

Coupled-cavity filter

A chain of metal resonant cavities joined by irises. Each coupling k(i,i+1) and the external Q at the ends follow from the prototype g values.

Unloaded Q (Qu)

Loss of a single resonator. The passband loss is about 4.343·Σg / (Δ·Qu) dB, so narrow filters need high-Q cavities.

Spurious passband

Line lengths repeat every half wavelength, so a transmission-line filter's response comes back at higher frequencies.

Group delay

How long the signal envelope takes to pass, −dφ/dω. It peaks near the cutoff, where the filter rings most.

Cutoff fc

Lowest frequency at which a waveguide mode propagates. Below it the field dies out (evanescent).

Dominant mode

The mode with the lowest cutoff, TE10 in a rectangular guide.

λg, vp, vg

Guide wavelength, phase velocity (faster than light) and group velocity (the speed of energy, slower than light).

From one antenna to a steerable beam

1. Every antenna element sends out the same wave. Far away the waves add up, and the result depends on the direction.
2. If all elements are in phase, the waves add best straight ahead (broadside): the main beam.
3. Delay each element a little more than its neighbour, by Δφ = −k·d·sinθ0, and the waves now line up in the direction θ0: the beam is steered without moving anything.
4. Beam switching picks one of a few fixed beams instead of setting any angle; MIMO uses several transmitters and receivers to build a much larger virtual array in software.

With your current settings:

Steering vs switching vs MIMO

Array terms

Array factor AF(θ)

The sum of all element signals in direction θ, Σ wn·e^(j·n·k·d·sinθ). The beam pattern is |AF|².

Broadside / endfire

Broadside is straight out of the array (θ = 0); endfire is along the array (θ = ±90°).

Beamwidth (HPBW)

Angle between the −3 dB points, about 0.886·λ / (N·d·cosθ0) radians for a uniform array.

Array gain

N elements add coherently: 10·log N dB more than one element.

Sidelobe

Smaller beams beside the main one (−13 dB for uniform weights). A taper lowers them but widens the main beam.

Grating lobe

A second full-size beam that appears when d > λ / (1 + |sinθ0|). Keep d ≤ λ/2 to scan anywhere.

Phase quantisation

A b-bit phase shifter only sets 2^b phases; the rounding error raises sidelobes and shifts the beam slightly.

Scan loss

The beam gets wider and the element gain drops as θ0 moves away from broadside.

MIMO and car terms

Butler matrix

A passive network of hybrids and fixed phase shifters: N inputs, N outputs, each input gives one fixed beam.

Crossover loss

Gain lost when the target sits between two switched beams (about 3.9 dB for touching DFT beams).

Virtual array

Every TX–RX pair acts as one element at position x_tx + x_rx, so Ntx × Nrx channels come from only Ntx + Nrx antennas.

TDM / DDM-MIMO

Ways to separate the transmitters: one after another in time, or with different Doppler (phase) codes at the same time.

Angular resolution

Smallest angle between two targets that still shows two peaks, about 2/Nv radians for λ/2 spacing.

Cascaded radar

Several radar chips (e.g. 4 × 3TX/4RX) sharing one clock (LO) to act as one big MIMO radar: an "imaging radar".

Corner radar

Short-range radar at a car corner, wide field of view, for blind spot, lane change and cross traffic.

How a current mirror copies a current

1. M1 is diode-connected: its gate is tied to its drain. Force Iref into it and it settles at exactly the VGS that carries Iref.
2. M2 shares that gate voltage and the same source (ground). Same VGS, same Vth, same size → the same current.
3. Make M2 wider and it carries more: Iout = (W2/W1)·Iref. This is how one reference feeds many bias currents on a chip.
4. It only works while M2 stays in saturation (Vout ≥ VGS − Vth). Below that it falls into triode and the current drops.
5. In saturation the current still rises a little with Vout (channel-length modulation), so the mirror is not a perfect current source: its output resistance is ro = 1/(λ·Iout).

With your current settings:

Mirror types

Terms

Current mirror

A circuit that copies a reference current to one or more outputs, scaled by transistor size.

Diode-connected

Gate tied to drain: VDS = VGS, so the transistor is always in saturation and behaves like a resistor of about 1/gm.

Mirror ratio

Iout/Iref = (W2/L2)/(W1/L1). Ratios are made from whole unit transistors for good matching.

Output resistance

ΔVout/ΔIout. Infinite for an ideal current source; ro for a single transistor.

λ (CLM)

Channel-length modulation, about λ0/L. Long transistors have smaller λ and higher ro.

Compliance (headroom)

Lowest output voltage at which the mirror still delivers its current.

Vov

Overdrive VGS − Vth. Small Vov saves headroom but makes the current more sensitive to Vth mismatch.

Cascode

A second transistor stacked on the output that holds the bottom one's VDS constant, multiplying the output resistance by gm·ro.

Mismatch

Random differences between "identical" transistors: ΔI/I ≈ −2·ΔVth/Vov in saturation.

Pelgrom's law

σ(ΔVth) = AVT/√(W·L): bigger transistors match better.

Common centroid

Layout that interleaves the unit transistors so gradients across the chip cancel.

INL / DNL

Integral and differential non-linearity of a DAC, in LSB: how far each output, and each step, is from ideal.

How a PN junction forms

1. Pure silicon has very few free carriers (ni ≈ 10¹⁰ cm⁻³). Doping adds them: boron gives holes (p-type), phosphorus or arsenic gives electrons (n-type).
2. Where p meets n, electrons diffuse into the p side and holes into the n side, and recombine.
3. The dopant atoms they leave behind are charged and fixed: a depletion region with a strong electric field.
4. The field pushes back on diffusion. Balance is reached at the built-in voltage Vbi ≈ 0.6–0.9 V.
5. An external voltage tips the balance: forward lowers the barrier (current e^(V/Vt)), reverse raises it (only leakage, until breakdown).

Your doping at a few bias points:

How to read a band diagram

Up means higher electron energy. Electrons live on or above Ec and roll downhill; holes live on or below Ev and float uphill. A sloped band means an electric field. The Fermi level EF marks how full the states are: close to Ec means n-type, close to Ev means p-type. In equilibrium EF is flat everywhere; an applied voltage V splits it by qV.

Where these junctions appear on this site

Junction terms

ni

Intrinsic carrier density of pure silicon, about 10¹⁰ cm⁻³ at room temperature.

Acceptor / donor

Dopant that takes an electron (boron → hole, p-type) or gives one (phosphorus → electron, n-type).

Ec, Ev, Eg

Conduction-band edge, valence-band edge and the band gap between them (1.12 eV in silicon).

Fermi level EF

Energy at which a state is half likely to be filled; it tells how n- or p-type the material is.

Vt = kT/q

Thermal voltage, 25.9 mV at 300 K: the natural voltage scale of carrier statistics.

Diffusion / drift

Carriers move from high to low concentration (diffusion) or are pushed by an electric field (drift).

Minority injection

In forward bias electrons enter the p side and holes the n side, where they are the minority and recombine.

Is

Reverse saturation current: tiny, set by ni², doping and diffusion lengths; doubles roughly every 5–6 °C.

Avalanche

Carriers gain enough energy in the field to knock out new electron-hole pairs, which multiply.

Zener breakdown

In very heavily doped junctions electrons tunnel straight through the thin barrier (below about 5 V).

MOS capacitor terms

Accumulation

Majority carriers (holes) gather at the surface; C ≈ Cox.

Depletion

Holes are pushed away; fixed charge forms a layer that grows with VG and lowers C.

Inversion

The surface holds more electrons than the bulk holds holes: it acts as n-type.

ψs

Surface potential: total band bending at the oxide interface.

φF

Fermi potential: (kT/q)·ln(NA/ni); strong inversion starts at ψs = 2φF.

VFB

Flat-band voltage: gate voltage that makes the bands flat (set by the work-function difference and oxide charge).

Cox

Oxide capacitance per area, εox/tox.

LF / HF C-V

At low frequency the inversion electrons follow the signal (C back to Cox); at high frequency they cannot, so C stays at its minimum.

Varactor

A voltage-controlled capacitor built from this structure; it tunes oscillators such as the radar VCO.

Why a transistor never turns fully off

1. Electrons in the source have a spread of thermal energies. Their number falls by 10× for every 60 meV of extra energy at room temperature (the Boltzmann tail).
2. The gate controls an energy barrier between source and drain. Only electrons above the barrier get through.
3. Each 60 mV the gate raises the barrier (at best) removes 90 % of the current. So below Vth, current falls exponentially, but never to zero.
4. To keep leakage small, Vth cannot go much below ~0.25–0.3 V, so VDD cannot go much below ~0.6–0.7 V. This "Boltzmann tyranny" is why supply voltages stopped shrinking.

Your transistor:

How the industry fought leakage

Node names like "3 nm" are marketing labels today; the real gate length is closer to 12–16 nm. What matters is how well the gate wraps the channel relative to its length (L/λ).

Leakage terms

Subthreshold swing SS

Gate voltage per decade of current below Vth; 60 mV/dec at 300 K is the physical limit.

Ion / Ioff

On current (speed) and off current (standby leakage) per µm of width.

Body factor n

1 + Cdep/Cox: the fraction of gate voltage lost to the depletion capacitance. Thin, fully depleted bodies get close to 1.

DIBL

Drain-induced barrier lowering: the drain voltage reduces Vth (mV per V).

LVT / SVT / HVT

Low, standard and high threshold transistors offered by the same process; designers mix them to trade speed for leakage.

GIDL

Gate-induced drain leakage: band-to-band tunnelling at the drain edge when the gate is strongly off.

Gate leakage

Electrons tunnelling through a very thin oxide; solved by high-k dielectrics (HfO₂) with a thicker physical layer.

Junction leakage

Reverse-biased source/drain diode current (see the PN junction tab).

Power gating

Switching whole blocks off with a high-Vth header or footer transistor to stop their leakage.

Structure terms

Scale length λ

Decay length of the gate's influence into the body; good control needs L ≳ 5λ.

FinFET

Channel stood up as a thin vertical fin, gate wrapped over three sides.

GAA / nanosheet

Gate-all-around: stacked horizontal sheets, each fully surrounded by the gate.

Fin / sheet pitch

Spacing between fins or stacks; sets how much width fits per unit area.

Effective width

Total gated channel perimeter; fins and stacked sheets give more of it per footprint.

Fully depleted

A body so thin that it is entirely depleted, which improves n and SS.

EOT

Equivalent oxide thickness: high-k layer expressed as the SiO₂ thickness with the same capacitance.

Three ways to store a bit

Your settings:

All three are built from the same MOSFET. SRAM uses it as a switch, DRAM as a valve for charge, and flash adds a second, floating gate that turns the threshold voltage itself into the stored value.

SRAM terms

Word line (WL)

Row signal that opens the access transistors of every cell in the row.

Bit lines (BL, BLB)

Column wires that carry the data in and out, as a complementary pair.

Precharge

Charging the bit lines to a known voltage before a read.

Sense amplifier

Fast latch that turns a small bit-line difference into a full logic level.

SNM

Static noise margin: size of the largest square in the butterfly plot's eye.

Read disturb

The 0 node is pulled up during a read; too much and the cell flips.

Cell ratio β

Pull-down / access strength; sets read stability.

DRAM and flash terms

Charge sharing

Cell and bit line settle to a common voltage; the bit line moves only by Cs/(Cs + Cbl) of the difference.

Refresh

Periodic read-and-rewrite of every row before its charge leaks away.

Retention time

How long a stored value survives without refresh (DRAM) or power (flash).

Floating gate / charge trap

Isolated storage layer for electrons; modern 3D NAND uses a silicon-nitride charge-trap layer instead.

Fowler-Nordheim tunnelling

Electrons tunnelling through a thin oxide under a very high field.

ISPP

Incremental step pulse programming: pulse, verify, pulse a bit higher.

SLC / MLC / TLC / QLC

1, 2, 3 or 4 bits per cell = 2, 4, 8 or 16 Vth levels.

Endurance

Number of program/erase cycles before the cell becomes unreliable.

ECC

Error-correcting code that repairs bits whose Vth drifted across a read reference.

3D NAND

Cells stacked in 100–300 layers around vertical channels.

The receive path, step by step

1. Antenna: collects the echo, often less than a picowatt.
2. LNA: amplifies it while adding as little noise as possible (optional at 77 GHz in CMOS).
3. Mixer: multiplies it by the transmit chirp (LO) and produces the beat frequency fb, a few MHz.
4. IF filter and amplifier: high-pass for leakage and near/far balance, low-pass against aliasing.
5. ADC: samples the beat signal, typically 12 bits at 20–50 MS/s.
6. FFT and detection: each target becomes a peak; peaks above the noise by about 13 dB count as detections.

Detection range with your receiver:

The radar now has two range limits: the IF bandwidth (fb must stay below 20 MHz, see the radar tab) and the echo power (SNR must stay above the threshold). The shorter of the two wins.

Receiver terms

Radar equation

Pr = Pt·G²·λ²·σ/((4π)³R⁴): echo power for a target with radar cross-section σ.

RCS σ

Radar cross-section: how big a target looks to the radar (car ≈ 10 m², pedestrian ≈ 0.5 m²).

kT

Thermal noise power density: −174 dBm per Hz at room temperature.

Noise figure NF

How many dB a stage worsens the signal-to-noise ratio.

Friis formula

Total noise factor; later stages count less because of the gain in front of them.

LNA

Low-noise amplifier: first gain stage, sets most of the noise figure.

LO

Local oscillator: the chirp from the PLL, used to mix the echo down.

IF

Intermediate frequency: the beat signal after the mixer.

Processing gain

SNR gained by the FFT (noise bandwidth 1/Tc) and by adding chirps coherently.

ADC terms

SAR

Successive approximation register: finds the code by binary search.

Capacitive DAC

Binary-weighted capacitors that produce each trial voltage.

Comparator

Decides whether the input is above or below the trial level.

LSB

Least significant bit: the smallest step, Vref/2^N.

SQNR / ENOB

Quantisation-limited SNR, 6.02N + 1.76 dB; ENOB is the effective number of bits including real noise.

Sample rate

Must be at least twice the highest beat frequency (Nyquist).

How a bipolar transistor amplifies

1. The emitter-base junction is forward biased: the emitter injects electrons into the base, e^(VBE/Vt) of them.
2. The base is so thin that almost all of them reach the far side before recombining.
3. The base-collector junction is reverse biased: its field sweeps them into the collector.
4. The base only supplies holes for the few lost electrons, so a small IB controls a large IC = β·IB.

Your transistor:

BJT or MOSFET?

Bipolar terms

Emitter / base / collector

Injector, thin control layer and the region that collects the carriers.

Forward active

EB forward, BC reverse: the normal amplifying mode.

Saturation

Both junctions forward biased; used as a closed switch, slow to leave.

β (hFE)

Current gain IC/IB, typically 100–1000.

gm

Transconductance IC/Vt: 38.6 mS per mA at room temperature.

Early voltage VA

Measure of how much IC rises with VCE; output resistance ro = VA/IC.

Gummel plot

log IC and log IB against VBE; their gap is β.

Kirk effect

At high current the base effectively widens into the collector and fT drops.

High-frequency terms

HBT

Heterojunction bipolar transistor: base made of a different semiconductor (SiGe, InP).

Ge grading

Germanium content rising across the base; creates a built-in drift field.

τB, τF

Base transit time and total forward transit time of the carriers.

fT

Transit frequency: where the small-signal current gain drops to 1.

fmax

Maximum oscillation frequency: where power gain drops to 1.

BiCMOS

Process with both bipolar transistors and CMOS on one chip.

Why the bandgap works

1. A forward-biased junction's voltage VBE drops by about 2 mV for every degree: CTAT.
2. Two junctions at the same current but with different areas differ by ΔVBE = (kT/q)·ln N, which grows with temperature: PTAT.
3. Add the PTAT term, scaled by K, to VBE. With the right K the slopes cancel.
4. The result sits near 1.2 V, the band-gap voltage of silicon extrapolated to absolute zero.

Your reference:

The same PTAT current is also a free temperature sensor: on-chip thermometers measure ΔVBE, and the "temperature" readout of a phone or CPU usually comes from such a circuit.

Reference terms

CTAT / PTAT

Complementary / proportional to absolute temperature.

Band-gap voltage

About 1.2 V: VBE extrapolated to 0 K; the sum the circuit settles at.

ppm/°C

Drift in millionths of the output per degree; good references reach 1–10 ppm/°C.

Curvature

The remaining bow because VBE is not perfectly linear in T.

Trimming

Adjusting K (with fuses or registers) on every chip after test.

Start-up circuit

Extra circuit that kicks the bandgap out of its all-zero state at power-on.

Op-amp terms

Differential pair

Two matched transistors sharing a tail current; responds to the input difference.

CMRR

Common-mode rejection: how much better the amplifier responds to the difference than to the common level.

Active load

Current mirror used as the load; converts the two currents into one output.

GBW

Gain-bandwidth product: open-loop gain × bandwidth, constant for a one-pole amplifier.

Phase margin

180° minus the loop phase lag at unity gain; 45° rings, 60° is a good target.

Miller compensation

Capacitor across the second stage that splits the poles and sets GBW.

Slew rate

Fastest output change, Iss/Cc, when the input step fully switches the pair.

Offset

Input voltage needed to make the output zero, caused by mismatch of the pair.

How latch-up starts and holds

1. Every CMOS inverter hides a PNPN stack: p+ (PMOS) → n-well → p-substrate → n+ (NMOS).
2. A disturbance injects current into the substrate; across Rsub it builds up 0.7 V.
3. The parasitic NPN turns on and pulls current through the n-well resistance, which turns on the PNP.
4. The PNP feeds the NPN's base: if βnpn·βpnp > 1, the loop keeps itself on after the trigger is gone.
5. The chip draws a large current until it is powered down, or burns.

Your design:

The same junctions explain both pages: the PN-junction tab shows why a diode conducts at about 0.7 V, and the BJT tab shows the gain β that makes the parasitic loop dangerous.

Latch-up terms

Thyristor (SCR)

PNPN device that, once triggered, stays on until its current falls below the holding current.

Parasitic bipolar

Unintended transistor formed by the wells and diffusions of CMOS.

Well / substrate tap

Contact that ties the well to VDD or the substrate to GND; more taps = lower resistance.

Guard ring

Ring of tap diffusion around a device that collects stray carriers.

Holding voltage

Voltage the latched path settles at; if it is below VDD the latch persists.

ESD terms

ESD

Electrostatic discharge: a sudden current from a charged person, tool or device.

HBM / CDM

Human-body model (100 pF, 1.5 kΩ) and charged-device model (the chip itself discharges, < 1 ns).

Primary diodes

Diodes from each pin to VDD and VSS that steer ESD current to the rails.

Power clamp

Large NMOS between the rails, turned on by the fast ESD edge through an RC timer.

Oxide breakdown

Permanent short through the gate oxide when the field exceeds about 10 MV/cm.

ESD window

The protection must turn on above the normal operating voltage but below the breakdown of what it protects.

The 15 steps shown here

Technologies compared

Every transistor on the other tabs is made this way. The PN junctions come from the implants, the gate oxide from oxidation, the MOS capacitor from gate + oxide + well, and the latch-up path from the wells and diffusions.

Process terms

Wafer

Thin disc of single-crystal silicon, today 300 mm in diameter.

Photoresist

Light-sensitive polymer; exposed areas dissolve in the developer (positive resist).

Mask / reticle

Quartz plate with the pattern of one layer, projected 4× reduced onto the wafer.

DUV / EUV

Deep-UV (193 nm, argon fluoride) and extreme-UV (13.5 nm) lithography light.

Plasma etch

Reactive ions accelerated toward the wafer etch straight down (anisotropic).

CVD / ALD / PVD

Ways to deposit films: chemical vapour, atomic layer by layer, physical sputtering.

Ion implantation

Dopant ions accelerated to keV energies and shot into the silicon.

Anneal

Heating to repair implant damage and put the dopant atoms on lattice sites (activation).

CMP

Chemical-mechanical polishing: flattens the wafer between layers.

STI

Shallow trench isolation: oxide-filled trenches that separate transistors.

LDD and spacer

Lightly doped drain extension next to the gate, and a nitride wall that offsets the heavy source/drain implant.

Silicide

Metal-silicon compound (NiSi) that lowers contact and gate resistance.

Damascene

Etch trenches into oxide, fill with copper, polish off the excess.

FEOL / BEOL

Front end of line (transistors) and back end of line (wiring).

From wafer to package

1. Wafer test: every die is probed; bad ones are marked.
2. Back-grind and dicing: the wafer is thinned and sawn into dies.
3. Die attach: the die is glued (or soldered) to a lead frame or substrate.
4. Interconnect: wire bonds, flip-chip bumps, or RDL in a fan-out package.
5. Encapsulation: mold compound or underfill protects die and joints.
6. Final test: electrical and RF test, burn-in for automotive parts, then tape and reel.

Package families

This continues the Process flow tab: that tab ends with copper wiring on the wafer; assembly connects that wiring to the outside world.

Assembly terms

Back-grinding

Thinning the wafer from the back side before dicing.

Scribe street

Empty lane between dies where the saw cuts.

Die attach

Bonding the die to the paddle or substrate with epoxy, film (DAF) or solder.

Free-air ball

Ball melted on the wire tip by an electric spark before the first bond.

Ball / stitch bond

First bond on the die pad, second bond on the lead.

Capillary

Ceramic tool that guides the wire and applies force and ultrasound.

EMC

Epoxy molding compound that encapsulates the die and wires.

Flip-chip and wafer-level terms

RDL

Redistribution layer: copper lines in polymer that move pads to new positions.

Passivation / PI

Nitride and polyimide layers that protect the chip and insulate the RDL.

UBM

Under-bump metallurgy: adhesion, barrier and wetting layers under the bump.

Bump / Cu pillar

Solder ball or copper post with a solder cap that forms the joint.

Reflow

Heating above the solder melting point; surface tension self-aligns the die.

Underfill

Epoxy under the flipped die that shares the thermal-expansion stress.

Fan-out

RDL extends beyond the die edge onto surrounding mold compound.

AiP

Antenna-in-package: radar antennas formed in the package RDL.

LiP

Launcher in package: a small transition in the package couples the signal into a hollow waveguide antenna above it.

Waveguide (WR-12)

Hollow metal pipe, 3.10 × 1.55 mm inside, that carries 60–90 GHz in the TE10 mode with very low loss.

TSV / hybrid bonding

Through-silicon vias and direct copper-to-copper bonding for 3D stacking.

When yield is low where there is no WAT data

1. Read the map: the shape of the failing area (edge, donut, center, line, repeat) points to the process step.
2. Rule out the tester: per-site yield, probe card, touchdown pattern. A test problem is not a fab problem.
3. Use data every die has: CP parametrics (ring oscillator, IDDQ, Vmin, RF gain, VCO frequency), calibrated against WAT where both exist.
4. Use denser fab data: inline thickness and CD maps, defect inspection scans, tool and chamber history (commonality).
5. Ask for more data: an engineering full-map WAT on the suspect wafers, nanoprobing and failure analysis on a failing die next to a good one.
6. Design it in next time: your own monitors inside the die, so every die carries its own PCM.
7. Protect the customer: GDBN, PAT and inking of the bad region until the cause is fixed.

Signature → likely cause → next step

Test terms

WAT

Wafer acceptance test: the fab's electrical test of test structures before the wafer ships.

PCM / testkey

Process control monitor: transistors, resistors, capacitors and chains placed in the scribe line.

Scribe line

The lane between dies that the dicing saw removes: free space for test structures.

CP / wafer sort

Circuit probe: every die is tested on the wafer with a probe card; results go into the bin map.

Bin

Test result category: pass, parametric fail, functional fail, contact fail.

Edge exclusion

Outer ring of the wafer (often 2–3 mm) that the fab does not guarantee.

Ring oscillator (RO)

Chain of inverters on the die whose frequency tracks transistor speed (Vth, Idsat).

IDDQ

Quiescent supply current: leakage of the whole die at rest; a defect often shows up as extra current.

Yield and screening terms

D0

Killer defect density per cm²: the main input of every yield model.

Kill ratio

Fraction of the defects of a type that actually make a die fail.

Commonality

Finding the tool, chamber or time that all bad lots share.

Nanoprobing

Landing fine probes on single transistors inside a die to measure Vth and Idsat directly.

EMMI / OBIRCH

Failure analysis methods that find leakage spots by emitted light or laser heating.

GDBN

Good die in bad neighbourhood: passing dies surrounded by failures are dropped.

PAT

Part average testing: outliers from the wafer's own distribution are dropped (AEC-Q001).

DPPM

Defective parts per million shipped: what the customer measures.

Latent defect

A defect that passes every test at time zero and fails later under voltage, current, heat or moisture.

Infant mortality

The early, falling part of the bathtub curve, caused mostly by latent defects.

Burn-in

Running chips hot (≈ 125 °C) at raised voltage for hours so weak ones fail in the factory.

Acceleration factor

How many hours of normal use one hour of stress is worth: AF = AF_T · AF_V.

TDDB

Time-dependent dielectric breakdown: traps build up in an oxide under field until it shorts.

Electromigration

Copper atoms pushed by the electron current; a narrowed line or via thins further until it opens.

HVST

High-voltage stress test: a short overvoltage step that breaks weak oxides during test.

WAT tells you the process was on target where it was measured. CP tells you every die. Use both: calibrate CP against WAT, then read the whole wafer.

How a pattern gets onto the wafer

1. Coat: a thin photoresist film is spun onto the wafer and baked.
2. Expose: the scanner images the mask (reticle) 4× reduced onto the wafer, one field at a time.
3. Post-exposure bake: acid made by the light diffuses and changes the resist chemistry.
4. Develop: the exposed (positive tone) resist dissolves; the pattern is left in resist.
5. Etch or implant: the resist protects what it covers, then it is stripped.

Scanners

Terms

NA

Numerical aperture: how wide a cone of light the lens collects. Water immersion lifts it above 1.

k1

Process factor in half-pitch = k1·λ/NA. The physical limit for lines and spaces is 0.25.

σ (partial coherence)

Size of the illumination; off-axis shapes (annular, dipole) push resolution further.

DOF

Depth of focus: the focus range over which the CD stays in spec, ≈ λ/NA².

Bossung plot

Printed CD versus focus for several doses: the process window.

LELE

Litho-etch-litho-etch: two masks, interleaved; overlay error becomes CD and space error.

SADP / SAQP

Self-aligned double / quadruple patterning: spacers on mandrels halve or quarter the pitch.

Cut mask

Extra mask that removes unwanted parts of the regular lines made by spacer patterning.

OPC

Optical proximity correction: serifs, hammerheads and biases on the mask compensate rounding and shortening.

Stochastics

Random photon and acid counts in tiny features: rough edges, missing or merged contacts.

LCDU

Local CD uniformity: random variation of neighbouring features.

Wear-out mechanisms

AEC-Q100 temperature grades

Terms

Black's equation

Electromigration lifetime falls with current density squared and rises exponentially as temperature drops.

Blech length

Below a critical product of current density and length, back-stress stops the atom flow: short lines are immune.

NBTI

Negative bias temperature instability: interface traps raise the PMOS threshold over time.

HCI

Hot carrier injection: fast electrons near the drain damage the oxide interface.

TDDB

Time-dependent dielectric breakdown of the gate or inter-metal dielectric.

HTOL

High-temperature operating life test: parts run at 125 °C and raised voltage for 1000 h.

Acceleration factor

Hours of use that one test hour represents: Arrhenius for temperature, plus a voltage term.

FIT

Failures in time: failures per 10⁹ device-hours. 1 FIT ≈ one failure in 114 000 device-years.

Weibull β

Shape of the failure distribution: < 1 early failures, 1 random, > 1 wear-out.

AEC-Q100

Stress-test qualification for automotive ICs from the Automotive Electronics Council.

From layout to masks

1. Draw: each layer of the layout is a set of polygons (the GDSII or OASIS file).
2. Check: DRC checks every width, space and enclosure; LVS extracts the circuit and compares it with the schematic.
3. Tape out: the checked layout goes to the mask shop, often after OPC.
4. Masks: each layer becomes one or more photomasks, used in the process flow.

Layers of this cell

Terms

Layout

The top-view drawing of every layer of a chip; a transistor is where poly crosses active.

GDSII / OASIS

File formats that hold the polygons of a layout.

λ rules

Scalable design rules: every width and space is a multiple of λ, half the minimum gate length.

Standard cell

A small fixed-height layout (inverter, NAND, flip-flop) with VDD and VSS rails at the top and bottom, so cells abut in rows.

Poly endcap

Extension of the gate beyond the active area, so the gate still cuts the channel if the masks are slightly misaligned.

DRC

Design-rule check: thousands of geometric rules that keep the layout manufacturable.

LVS

Layout versus schematic: the extracted devices and connections must match the circuit.

Well tap

Contacts that tie the n-well to VDD and the substrate to VSS, against latch-up.

One radar frame, step by step

1. Chirps: the transmitter sends a burst of fast chirps; each echo is mixed down to a beat signal and sampled by the ADC.
2. Range FFT: the beat frequency of each target becomes a peak at its range bin.
3. Doppler FFT: across chirps, the phase of each range bin rotates with the target's speed.
4. CFAR: an adaptive threshold separates targets from noise and clutter.
5. Angle FFT: across the virtual antenna channels, the phase step gives the direction.
6. Point cloud and tracking: detections with range, speed and angle feed the tracker and the sensor fusion.

This radar

Terms

Data cube

Samples × chirps × channels of one frame; the three FFTs run along its three axes.

Range bin

One output of the range FFT: a slice of distance ΔR = c/2B wide.

Doppler bin

One output of the Doppler FFT: a slice of radial speed.

Window

Taper applied before an FFT to lower sidelobes, at the cost of resolution.

CFAR

Constant false-alarm rate: the threshold follows the local noise so the false-alarm rate stays fixed.

Clutter

Echoes from things that are not targets: road, guardrails, buildings; mostly at zero speed.

Point cloud

The list of detections with range, speed, angle and amplitude for each frame.

Integration gain

Coherent FFTs over N samples raise the signal-to-noise ratio by 10·log10 N.

From measurement to action

1. Sample: a few wafers per lot and a few sites per wafer are measured after key steps.
2. Measure: CD-SEM, scatterometry, overlay, film thickness and defect inspection.
3. Chart: each result goes on a control chart with limits from the normal behaviour of the process.
4. React: a rule violation holds the lot or the tool (out-of-control action plan).
5. Correct: run-to-run controllers feed the measurements back into the next lot's recipe.

Typical inline measurements

Terms

CD

Critical dimension: the width of the smallest lines or holes of a layer.

LER / LWR

Line-edge and line-width roughness: the 3σ variation of an edge or of the width along a line.

Scatterometry

Optical CD: measure the spectrum reflected by a grating and find the profile whose simulated spectrum fits it.

Overlay

Misalignment between two patterned layers, corrected by the scanner per lot.

Control limits

±3σ of the process when it is stable; not the same as the specification limits.

Western Electric rules

Patterns on a control chart that are unlikely by chance and signal a change in the process.

Cp / Cpk

Process capability: how many 3σ fit between the mean and the nearest spec limit.

Run-to-run (R2R)

Feedback that adjusts the recipe of the next lot from the measurements of earlier lots.

Where the heat goes

1. Transistors: switching and leakage turn almost all electrical power into heat in a thin layer at the top of the silicon.
2. Die and TIM1: heat crosses the silicon and the thermal interface into the lid.
3. Lid and TIM2: the copper lid spreads it out; a second interface couples it to the heat sink.
4. Heat sink: fins, a fan or a liquid loop hand it to the air or the coolant.
5. Board path: a smaller part flows down through the substrate, the solder balls and the board.

Typical thermal resistances

Terms

Junction temperature Tj

Temperature of the transistors; reliability and leakage depend on it, limits are 85–125 °C.

Thermal resistance θ

Temperature rise per watt of heat flow, in °C/W: the thermal version of Ohm's law.

θJA, θJC

Junction to ambient, junction to case: the standard package figures in a data sheet.

TIM

Thermal interface material: grease, solder or liquid metal that fills the gap between two surfaces.

Heat spreading

Sideways conduction in the silicon and the lid that lowers the peak temperature of small hot blocks.

Hot spot

A small block with high power density, much hotter than the die average.

Thermal impedance Zth(t)

Temperature rise after a power step, as a function of time; each layer adds a time constant τ = R·C.

Throttling

Lowering clock frequency and voltage when Tj reaches its limit, to stay safe.

The four building blocks of every process flow

1. Add: deposition grows films: oxidation, PVD, CVD, ALD, epitaxy, electroplating.
2. Pattern: lithography defines where (see the Lithography tab).
3. Remove: etch transfers the pattern; CMP flattens the surface.
4. Modify: implantation and anneals change the doping and the crystal.

Deposition methods compared

Terms

Czochralski (CZ)

Growing a single-crystal ingot by slowly pulling a rotating seed out of molten silicon.

Segregation coefficient k₀

Ratio of dopant concentration in the crystal to that in the melt; below 1, the melt gets richer as the ingot grows.

Epitaxy

Growing a crystalline layer that continues the lattice of the substrate.

SOI

Silicon on insulator: a thin silicon layer on a buried oxide, made by Smart Cut (hydrogen implant, bond, split).

Conformality

How evenly a film covers the top, sidewalls and bottom of a feature; step coverage is bottom over top thickness.

ALD

Atomic layer deposition: alternating self-limiting surface reactions add one monolayer per cycle.

Anisotropy, ARDE

Etching straight down rather than sideways; aspect-ratio-dependent etching makes narrow features etch slower (RIE lag).

Dishing, erosion

CMP artefacts: wide metal lines sag in the middle, dense arrays lose oxide and metal together.

Where variation comes from

1. Wafer to wafer, lot to lot: tool drift, chamber differences: global shifts of all transistors.
2. Across the wafer: thickness and dose gradients from centre to edge.
3. Within the die: layout context, stress, density effects.
4. Device to device: random dopants, line-edge roughness, metal-gate grains: pure chance, uncorrelated even for neighbours.

Typical sign-off corners

Terms

Global variation

Shifts every transistor on a die the same way; captured by process corners.

Local mismatch

Random differences between identical neighbouring transistors.

Pelgrom law

σ(ΔVt) = A_Vt / √(W·L): mismatch averages out over a larger area.

Process corner

A model file at about ±3σ of the global spread, such as SS or FF.

PVT

Process, voltage and temperature: the three axes of sign-off.

Monte Carlo

Simulating many random samples of the device parameters to get a distribution.

SNM

Static noise margin: how much noise an SRAM cell tolerates before it flips; the largest square in the butterfly curve.

Sigma

Mean over standard deviation of a margin; a gigabit memory needs more than 6σ per cell.

The digital flow in one line each

1. RTL: the behaviour written in Verilog or VHDL, verified by simulation.
2. Synthesis: RTL mapped to standard cells of the target library under timing constraints.
3. Place and route: cells placed in rows, clock tree built, wires routed in the metal layers.
4. Sign-off: static timing at all corners, power and IR drop, DRC and LVS.
5. Tape-out: the GDS/OASIS file goes to the mask shop; first silicon follows months later.
6. Test: scan patterns and memory BIST screen every die on the tester.

Typical numbers for a large SoC

Terms

RTL

Register-transfer level: registers and the logic between them, described in a hardware language.

Standard cell

A pre-designed gate or flip-flop of fixed height from the foundry library.

Clock tree

Buffers and wires that deliver the clock to every flip-flop with small skew.

STA, slack

Static timing analysis checks every path; slack is the margin left before the deadline, negative means a violation.

Setup, hold

Data must arrive before the next clock edge (setup) and must not change too soon after it (hold).

DFT, scan

Design for test: flip-flops are chained into shift registers so a tester can set and read every state.

ATPG

Automatic test pattern generation: finds input patterns that expose each modelled fault.

DPPM

Defective parts per million that escape test and reach the customer.

Inside a SerDes link

1. Serializer: wide parallel data becomes one fast bit stream.
2. TX driver + FFE: pre-distorts the symbols to fight the channel.
3. Channel: package, board, connector, cable; loss grows with frequency.
4. RX CTLE + DFE: boosts high frequencies and cancels the tail of earlier symbols.
5. CDR and slicer: recovers the clock and decides each symbol.
6. Deserializer + FEC: back to parallel data, errors corrected.

Typical links

Terms

Insertion loss

Attenuation of the channel in dB; skin effect and dielectric loss make it grow with frequency.

ISI

Inter-symbol interference: each smeared pulse leaks into its neighbours.

Eye diagram

All symbol periods overlaid; the open area is the margin for the decision.

FFE, CTLE, DFE

Feed-forward, continuous-time linear and decision-feedback equalizers.

PAM4

Four amplitude levels, two bits per symbol, three eyes each a third as tall.

Jitter

Timing uncertainty of the edges: random (Gaussian) plus deterministic (bounded).

BER

Bit error ratio; 10⁻¹² before FEC is a classic target.

UCIe

Universal Chiplet Interconnect Express: a standard parallel die-to-die interface for chiplets.

Why SiC is hard to make

1. No melt: SiC sublimes instead of melting, so crystals grow from vapour at about 2300 °C, a few hundred times slower than silicon.
2. Hard: almost as hard as diamond; slicing and polishing take far longer.
3. Dopants do not move: implants need 500 °C and activation needs about 1700 °C.
4. Interface: the oxide traps carbon-related defects that slow the channel.
5. Defects: dislocations from the crystal can kill or slowly degrade devices.

Silicon, SiC and GaN

Terms

4H-SiC

The hexagonal polytype of silicon carbide used for power devices; the stacking repeats every four layers.

PVT

Physical vapour transport: SiC powder sublimes at the hot bottom of a graphite crucible and condenses on a cooler seed.

Micropipe

A hollow screw dislocation running through the crystal; once the main killer defect, now nearly eliminated.

BPD

Basal plane dislocation; under bipolar current it can expand into a stacking fault that raises the resistance.

Step-flow epitaxy

Growth on a wafer cut 4° off axis, so atoms attach at step edges and copy the 4H stacking.

Critical field

Electric field at which avalanche breakdown starts; ten times higher in SiC than in Si.

Baliga figure of merit

ε·μ·Ec³: the lower limit of specific on-resistance for a given breakdown voltage.

Dit

Interface trap density; traps near the conduction band capture channel electrons and lower the mobility.

The three faces of the Miller capacitance

1. Amplifiers: Cgd between input and an inverting output looks (1 + A) times larger at the input and cuts the bandwidth.
2. Switching: while the drain voltage swings, all gate current goes into Cgd and the gate voltage stays flat: the Miller plateau.
3. Half-bridges: a fast drain-voltage edge pushes current through Cgd into the gate of an off transistor and can turn it on.

Data-sheet capacitances

Terms

Cgd (Miller capacitance)

Capacitance between gate and drain, from the gate overlapping the drain and the drift region.

Miller effect

A capacitor across an inverting gain stage appears multiplied by (1 + A) at its input.

Miller plateau

The flat part of the gate voltage during switching, while the gate current charges Cgd.

Gate charge Qg

Total charge the driver must deliver to switch the transistor on; sets the driver power Qg·Vdrv·f.

Switching loss

Energy lost while voltage and current overlap during a transition; much of it during the Miller plateau.

False turn-on

Unwanted turn-on of an off transistor by dV/dt through Cgd, causing shoot-through.

Miller clamp

A small switch in the driver that shorts gate to source with very low impedance while the transistor is off.

Cascode

A common-gate transistor stacked on the input transistor that holds its drain still and removes the Miller multiplication.

How a MOSFET breaks down

1. Avalanche: the reverse-biased drain junction holds the field; above a critical field, carriers knock out new electron-hole pairs and the current multiplies.
2. Snapback: the generated holes flow to the body contact and raise the body potential; the source-body junction turns on, the parasitic NPN conducts and the drain voltage collapses.
3. Punch-through: in a short channel the drain depletion reaches the source, the barrier disappears and current flows below the channel.
4. Gate oxide: the thin oxide breaks down at about 10–15 MV/cm, instantly or after long stress (TDDB).

Typical numbers

Terms

Avalanche breakdown

Runaway carrier multiplication when the junction field exceeds about 3–5 × 10⁵ V/cm in silicon.

Impact ionization

A fast carrier hits the lattice hard enough to create a new electron-hole pair.

Multiplication factor M

Ratio of output to input current, M = 1/(1 − (V/BV)ⁿ), growing without limit near BV.

Substrate current

The holes generated at the drain, flowing to the body contact; a monitor of hot-carrier stress.

Snapback

Parasitic bipolar turn-on that drops the drain voltage to a holding voltage; used on purpose in ESD protection.

Punch-through

Merging of the source and drain depletion regions in a short channel, so the gate loses control.

Fowler–Nordheim tunnelling

Electrons tunnelling through the triangular oxide barrier at high field.

Hard breakdown

A conducting path of defects forms across the oxide and the gate shorts to the channel.