00
Why BIST: what it replaces
Testing a 77 GHz transceiver the conventional way needs mmWave power meters or spectrum analysers per Tx, a calibrated 77 GHz source and noise source for the Rx, frequency-extension heads, and an RF-capable load board. Each channel is measured one after another, with instrument settling and switching in between. The equipment is expensive, needs calibration, is hard to run multi-site, and in practice takes up most of the test time.
BIST vs BISM
BIST (Built-In Self-Test) and BISM (Built-In Self-Measurement) use the same on-chip stimulus, loopback paths, detectors, ADCs and counters. What differs is the result. BIST answers “is this part good?” with pass/fail against a limit. BISM answers “what is the value?” with a calibrated number (Tx power in dBm, Rx gain and phase, NF, LO frequency). That number feeds eFuse trims, calibration tables, correlation against the RF tester, and in-field trend monitoring. Most of the recipes on this page are BISM, and the pass/fail step is simply a limit applied to the measured value.
| BIST: self-test | BISM: self-measurement | |
|---|---|---|
| Output | Pass/fail, fault flag | Value with units and accuracy |
| Needs absolute accuracy? | Only enough to hold the limit with guard band | Yes: correlated to golden units, trimmed references |
| Used for | Screening, binning, start-up checks, safety fault detection | Trim, calibration LUTs, correlation, drift and trend tracking |
| Example | “Tx1 power within 12 ± 1.5 dBm” → pass | “Tx1 = 12.4 dBm at 85 °C” → power LUT entry |
With BIST the chip is its own instrument. The ATE only supplies power, a reference clock and a digital interface (SPI/I²C, GPIOs). It loads a test firmware, starts a test list, and reads back results the chip has already computed.
| What the ATE used to provide | On-chip replacement |
|---|---|
| 77 GHz power meter (Tx Pout) | Output coupler + square-law power detector → aux ADC |
| 77 GHz signal generator (Rx gain) | Tx signal coupled into Rx via loopback, offset in frequency by an on-chip modulator |
| Noise source (NF) | On-chip hot/cold noise source, or "cold" method using known gain |
| Spectrum analyser / frequency counter (LO) | ÷N prescaler + counter referenced to the crystal; PLL phase-error monitor |
| Phase-calibrated VNA (Tx/Rx phase) | Loopback phase read from the Rx FFT bin, relative between channels and codes |
| Baseband AWG + digitiser (IF chain, ADC) | IF test-tone DAC/DDS injected before the IF chain; the main ADC + FFT measure it |
| DMM on supplies and temperature | Aux SAR ADC with analog mux, temperature sensors, bandgap cross-check |
01
Test architecture: where the signals go
Six test paths (A–F) sit next to the normal signal chain. Every test is one of them, or a combination: a stimulus enters at one point, and a measurement block reads it out at another.
| Path | Stimulus | Route | Read by | Main use |
|---|---|---|---|---|
| APower detect | Tx itself | PA → coupler → forward/reverse detector | Aux ADC | Tx Pout, PA gain codes, ball/antenna open (reflected) |
| BRF loopback | Tx + modulator offset f_m | Tx coupler → atten → mod → Rx coupler → LNA → mixer → IF → ADC | Main ADC + FFT | Rx gain/phase, Tx phase rotator, Tx-to-Tx phase, I/Q, linearity, end-to-end |
| CIF loopback | DDS tone | IF DAC → IF chain input | Main ADC + FFT | HPF/LPF response, VGA steps, ADC SNR/SFDR, channel matching in baseband |
| DLO monitor | VCO itself | VCO ÷N → counter (gated by ref); PLL phase-error tap | Counter / digital | Start frequency, slope, ramp linearity, lock, VCO range |
| ENoise source | Hot/cold noise | Noise source → LNA input | Main ADC + FFT (noise floor) | Rx noise figure (Y-factor) |
| FSensors | DC nodes | Mux → aux ADC (how the muxes work) | Aux ADC | Supplies, temperatures, bandgap cross-check, detector offsets |
02
Test muxes: connecting every sub-block to the instruments
The chip has only a few instruments (an aux ADC, the main ADCs with FFT, a frequency counter, the power detectors), but hundreds of nodes to check: every supply, reference, bias current, detector, tuning voltage and clock. Test multiplexers connect each sub-block to one of the instruments, one at a time. They are the routing behind paths A–F above, and they exist in every domain: DC analog, IF, 77 GHz RF, clocks and digital.
Kinds of test mux
| Mux type | Circuit | Carries | Key specs | Watch out for |
|---|---|---|---|---|
| DC / analog test mux | Transmission gates or T-switches, thick-oxide where the node can exceed the core supply | Supplies, references, bias voltages, detector and temperature outputs | Ron 100 Ω–5 kΩ, I_off < 1 nA per switch at 150 °C, full-range pass | Leakage at hot, charge injection on high-Z nodes, back-powering a domain that is off |
| Current test mux | Mirror copy of a bias current switched to the ATB (into a sense resistor or the ATE PMU) | LNA, mixer, PA, CP and DAC reference currents | Mirror ratio accuracy 1–2 %, compliance voltage | Switching the mirror must not disturb the real bias; copy, never break the bias line |
| IF / baseband mux | CMOS switches with bootstrapped or constant-Vgs gates at the TIA output or ADC input | Test tone into the IF chain; ATB, short or VREF into the ADC | Bandwidth > 2× IF (20–40 MHz), HD3 < −70 dBc, channel isolation > 60 dB | Nonlinear Ron adds distortion; unused inputs must be grounded, not floating |
| RF loopback switch | Series–shunt FET switches, often with a λ/4 line so the shunt FET looks open when on | Tx coupler to modulator to Rx coupler (SP4T / splitter) | Insertion loss 2–4 dB (inside the level plan), isolation > 40 dB when off | Off-state leakage from Tx to Rx lands at DC (harmless) but loads the couplers; FET capacitance detunes the path |
| Clock / observe mux | Glitch-free clock mux (synchronised select), CML to CMOS converters, dividers before the mux | VCO ÷N, reference, ADC and CPU clocks, lock detect to counter or GPIO | Duty cycle, added jitter, fan-out load on the VCO divider | A glitch on switching can clock state machines wrongly; divide first so the mux never sees 20 GHz |
| Digital test mux | Standard-cell 2:1 muxes controlled by test mode | Scan paths, test clocks, bypasses (see the DFT page) | Timing in both modes | Mux in the clock path adds skew; test mode must be impossible to enter in the field |
Switch circuits that keep the measurement honest
Leakage error V_err = N_off · I_off(T) · (R_on + R_src) I_off roughly doubles every 10 °C
e.g. 32 switches × 0.5 nA at 150 °C × 20 kΩ = 0.32 mV (≈ 1/3 LSB of a 12-bit, 1.2 V ADC)
Settling τ = (R_on + R_src) · C_bus , C_bus = N · C_off + C_wire
e.g. (2 kΩ + 20 kΩ) × (32 × 20 fF + 1 pF) ≈ 36 ns → 12-bit settling ≈ 9τ ≈ 0.3 µs
Charge injection ΔV = Q_inj / C_node (large on a 1–10 pF bandgap or loop-filter node)
Isolation (RF) off-state S21 < −40 dB so the "off" loopback stays below the Rx noise floor
What each sub-block brings to the bus
| Sub-block | Node(s) routed | Through | Measured by | Gives |
|---|---|---|---|---|
| Bandgap | VBG, PTAT voltage, trim DAC output | Local mux → ATB → top mux | Aux ADC, then one precision ATE voltage on the test pin | BG trim; reference for everything else |
| LDOs | Each Vout (÷2 divider for 1.8/3.3 V), dropout at forced load | Local mux, Kelvin F/S for load steps | Aux ADC, ATE PMU forcing load current | Output trim, load regulation, UV/OV threshold check |
| LNA / mixer | Bias current copy, gate bias, TIA output common mode | Current mux → sense R → ATB | Aux ADC | Bias trim; open or shorted device shows as wrong current |
| PA | Drain current sense, fwd / rev detector, local temperature diode | Local mux → ATB | Aux ADC (PA on minus PA off) | Tx power, gain codes, reflected power, PA temperature |
| VCO / PLL | Vtune (buffered), CP up and down currents, divided VCO | Buffer → ATB; ÷N → clock mux | Aux ADC, frequency counter | Band calibration, Kvco, CP mismatch, lock and band edges |
| IF chain | Test tone in, VGA output DC offset per gain code | IF input mux, ADC input mux | Main ADC + FFT | Filter corners, gain steps, offset per code |
| ADC | Short (offset), VREF (gain), ATB (DC linearity) | ADC input mux | ADC itself | Offset and gain calibration; DC check of any ATB node at full ADC resolution |
| Rotator DAC | DAC output current per code | Current mux into a sense resistor | Aux ADC | DAC INL / DNL and bow before the RF phase sweep |
| Digital / clocks | Clock domains, lock detect, internal status | Clock / observe mux | Counter, GPIO | Clock frequencies, PLL lock, debug |
Check the path before the block. Start every test session by routing ground, VREF and a known divider through each mux level to the aux ADC. That measures the path offset, gain and leakage, and proves the selects work. A block result is only trusted after its path passes this check. The same readback runs in the field as a safety mechanism.
Control and safety
- One-hot selects with break-before-make. Only one source on a bus segment at a time. The decoder opens the old switch before closing the new one.
- Reset state is all off, bus grounded. The ATB is tied to ground by a shunt switch in mission mode, so it can't pick up or inject noise.
- Test mode is locked. Entering it needs a key sequence (and on some parts a test pin), so a software error in the car can't open a test path.
- Readback. The safety monitor reads the mux control register (or its CRC) periodically; a path that is on unexpectedly is a fault.
- In-field use. The same muxes serve the runtime monitors (supplies, temperatures, detector) between frames, so their switching is verified every drive cycle.
Problems caused by test muxes
| Problem | Why it happens | How to avoid or catch it |
|---|---|---|
| Reading is wrong only at hot | All N off-switches on the bus leak; the sum flows through the on-switch and the source resistance | Hierarchical bus (short local segments), T-switches, keep N small per segment; measure the "all off" leakage at 150 °C |
| Node disturbed when selected | Bus capacitance and charge injection hit a high-impedance node (bandgap, loop filter) | Buffer before the mux; wait for settling; measure twice and compare |
| Spurs in normal operation | A long ATB wire couples digital or supply noise into VCO or LNA bias through the off switches | T-switch grounding, route the ATB away from RF, ground the whole bus in mission mode |
| Back-powering | A node in a powered domain reaches a switch in an unpowered domain through its well or ESD diode | Switch supplies from the higher domain, or isolation cells; check with power-domain-aware verification |
| Shorted nodes while switching | Make-before-break briefly connects two sources on the bus | Break-before-make in the select logic (one-hot with a gap) |
| Mux left on in the field | Stuck register bit or software error keeps a test path enabled | Test mode behind a key sequence; safety monitor reads back the mux register (ISO 26262); default all-off at reset |
| ESD / overvoltage from the test pin | The test pin connects straight to internal nodes | Series resistor and ESD clamp on the pin, thick-oxide switches, pin disabled after test |
| Wrong result traced to the mux, not the block | A mux fault looks exactly like a block fault | Self-check the path first: route GND, VREF and a known divider through every mux level before measuring blocks |
03
Generating stimulus on-chip
The FMCW loopback problem, and the fix
In FMCW, Tx and Rx use the same chirping LO. A straight Tx → Rx loopback has almost zero delay, so its beat frequency is about S·τ ≈ 0 Hz: it lands at DC and the HPF removes it. A useful loopback therefore has to be offset in frequency by a known f_m (typically 0.5–5 MHz), so that it appears as a clean tone in a chosen IF bin. The same fact is also useful: loopback leakage when the path is "off" also lands at DC, where it is harmless.
| Offset method | How | Spectrum at IF | Trade-off |
|---|---|---|---|
| BPSK modulator | 0/180° switch in the loopback, toggled by a square wave at f_m (ref ÷ M) | ±f_m, ±3f_m (−9.5 dB), ±5f_m …; carrier suppressed | Simplest. ±f_m both appear, so I/Q image can't be separated from the tone |
| SSB / serrodyne (reuse the phase rotator) | Step the loopback or Tx phase rotator 0 → 360° every 1/f_m in K steps (e.g. K = 8 or 16) | +f_m dominant; spurs at f_m·(1 ± nK) | No extra RF block. Single sideband, so image at −f_m directly measures I/Q imbalance |
| Dedicated I/Q upconverter | Small SSB mixer driven by I/Q tones at f_m | +f_m, image < −30 dBc | Cleanest tone, more area; mixer itself needs checking |
| Delay line | Real delay τ gives f_b = S·τ | f_b tone | On-chip τ is too small; practical only as an off-chip load-board trace (also tests the balls) |
| IF DDS (path C) | Digital synthesiser → DAC → IF input | any tone(s) in DC–20 MHz | Tests only IF + ADC, not the RF |
| Noise source (path E) | Forward-biased diode/transistor (hot) vs matched termination (cold) | white noise | ENR must be characterised; drifts with temperature |
Level plan for loopback B (typical)
P_Tx out +12 dBm
Tx output coupler (weak) −20 dB ← costs ≈0.05 dB of Pout
Programmable attenuator −0 … −30 dB
Modulator loss (SSB / BPSK 1st) −4 … −6 dB
Rx input coupler −20 dB ← adds ≈0.2–0.4 dB to NF
─────────────────────────────────────────────
At LNA input ≈ −34 … −64 dBm (well below Rx P1dB ≈ −10 dBm)
Set the attenuator so the tone sits about 10–20 dB below ADC full scale. The ratio of tone to noise in one FFT bin is then 50–70 dB, so a single chirp is enough for gain and phase accuracy better than 0.05 dB / 0.3°.
04
Measuring on-chip: four instruments in silicon
1 · Power detector + aux ADC
A square-law (diode-connected MOS or bipolar) or log detector sits on a weak coupler at the PA output. Its DC output is proportional to RF power and goes to a 10–12 bit SAR ADC through the analog mux. A second detector on the reverse port measures reflected power.
V_det = V_off + k · P_RF (square-law region)
P_out[dBm] = 10log((V_on − V_off)/k) + C_cpl
Differential: V_off = V_det with PA off → removes offset/drift
Always measure PA on minus PA off, and ratio against an on-chip reference voltage, so that offset and ADC gain errors cancel.
2 · Main Rx ADC + FFT as a vector receiver
The normal Rx chain acts as a vector network analyser receiver. Pick f_m so it falls exactly on a bin (f_m = k·F_s/N) to avoid leakage between bins, and use a rectangular window.
X_i[k] = FFT(x_i)[k] channel i, tone bin k
A_i = 2|X_i[k]| / N amplitude
φ_i = arg X_i[k] phase
ΔG_i = 20log(A_i/A_ref) relative gain
Δφ_i = φ_i − φ_ref relative phase
Noise = mean |X[j]|², j ≠ tone, harmonics, DC
3 · Frequency counter and PLL monitor
A prescaler divides the VCO (÷N, e.g. 256 at 20 GHz ≈ 78 MHz). A counter gated by the crystal counts it. The resolution at RF is set by the gate time:
f_RF = 4 · N · count / T_gate
Δf_RF = 4 · N / T_gate
T_gate = 1 ms → 1.0 MHz resolution at 77 GHz
T_gate = 10 ms → 0.1 MHz
For slope and linearity during a chirp, read the PLL phase error (the ΣΔ loop error or TDC output in an ADPLL). Integrated frequency error along the ramp gives the RMS nonlinearity directly, without a counter.
4 · Aux ADC as DMM
The same aux ADC reads temperatures (PTAT diodes near each PA, digital, VCO), every supply rail through dividers, LNA and PA bias currents (through sense resistors), and a second bandgap. The two bandgaps checking each other is what makes the aux ADC trustworthy as a reference.
- Resolution
- 10–12 bit, ≈1 mV LSB
- Temp accuracy
- ±2–5 °C after 1-point trim
- Conversion
- ≈1–5 µs per channel
05
Test recipes: stimulus → path → measurement → result
| Test | Path | Chip does | Computes | Feeds back |
|---|---|---|---|---|
| Tx output power | A | PA on/off per Tx, per gain code; sweep 3 frequencies across the band | P_out[dBm], gain-code step error, flatness | Tx power LUT, pass/fail |
| Tx ball / antenna open | A | Read reverse detector | Return loss estimate | Pass/fail (needs the load board termination) |
| Tx phase-rotator linearity | B | Step all 64 codes on one Tx, capture loopback tone phase and amplitude | Phase INL/DNL, AM/PM per code | Code-correction LUT |
| Tx-to-Tx phase / gain | B | Enable each Tx in turn into the same Rx | ΔG, Δφ vs Tx1 | MIMO / beamforming calibration |
| Rx gain and Rx-to-Rx match | B | One Tx into all Rx at once, same capture | Absolute gain (via A), ΔG_i, Δφ_i | Rx calibration vector |
| I/Q imbalance | B SSB | Tone at +f_m, measure image at −f_m | IRR, ε (gain), θ (phase) | DFE I/Q correction coefficients |
| Rx compression | B | Sweep attenuator, track output vs input | P1dB (input-referred) | Pass/fail |
| Rx noise figure | E or B+noise | Hot/cold captures, or cold only plus known gain | NF [dB] | Pass/fail, NF bins |
| IF filter response | C | Sweep DDS 50 kHz–20 MHz, each HPF/LPF setting | Corner freq, ripple, group delay | Filter trim (R/C codes) |
| VGA gain steps | C | Fixed tone, step all gain codes | Step error, monotonicity | Gain LUT |
| ADC dynamic performance | C | Near-full-scale tone, long capture | SNR, SFDR, THD, ENOB | Pass/fail |
| LO frequency / range | D | Force VCO to band edges, count | f_min, f_max, K_VCO | VCO band-select trim |
| Chirp slope / linearity | D | Run chirp, log PLL phase error along the ramp | Slope error, RMS/peak nonlinearity | Pre-distortion coefficients |
| Supplies, temps, bandgap | F | Scan the mux | V, T, BG1 vs BG2 | Temp sensor trim, BG trim |
Key recipes in detail
Rx gain & phase match (path B)
- Enable Tx1 at a fixed power code; enable the loopback, attenuator code for about −15 dBFS at the ADC.
- Start the SSB modulator at f_m = k·F_s/N (e.g. 1.25 MHz).
- Run a CW or shallow chirp. Capture N samples on all Rx at the same time.
- FFT; read X_i[k] for each Rx. Average 8–16 chirps for margin.
- ΔG_i, Δφ_i relative to Rx1 → write the calibration vector; compare with limits.
All Rx share one input signal and one LO, so the loopback's own variation cancels in the relative result.
Noise figure without a noise source
1. Known input tone P_in at LNA (from A + loopback cal)
2. G_total = P_tone,out − P_in (from FFT)
3. Disable loopback (input = 50 Ω, T0)
4. N_out = mean noise PSD in bins [dBFS/Hz → dBm/Hz]
5. NF = N_out − G_total − (−174 dBm/Hz)
Accuracy depends on the absolute value of P_in. Correlate it to lab NF on golden units, and track it with a guard band of about ±1 dB. With an on-chip hot/cold source, use Y = N_hot/N_cold, NF = ENR − 10log(Y−1).
Tx phase-rotator sweep
for code c = 0..63:
set ROT(Tx_n) = c ; capture ; X[k]
φ(c) = arg X[k] − arg X_c=0[k]
A(c) = |X[k]| / |X_c=0[k]|
INL(c) = φ(c) − c · 5.625°
→ store corrected code map c' = argmin |φ(c) − target|
About 64 captures of 50 µs each is roughly 3 ms per Tx. On an RF ATE this would need a phase-coherent receiver on every Tx ball.
Chirp linearity (path D)
- Program the production chirp profile (slope, B, T_ramp).
- Stream the PLL phase error e[n] into memory during the ramp.
- Integrate to frequency error Δf[n]. Fit and remove a line to get the nonlinearity residual.
- Report RMS and peak residual (in kHz and % of B) inside the ADC window only, plus settling time after reset.
The counter (1 ms gate) checks the absolute start and stop frequency against the 76–81 GHz band edges.
06
Feeding results back: pass/fail, trim, calibration
Each measurement ends up in one or more of three places. The same code runs at wafer test, final test, module EOL and in the field.
| Destination | What goes there | When | Mechanism |
|---|---|---|---|
| Result registers → ATE | Measured values plus pass/fail bits against limits in the test FW | Every test | ATE reads over SPI; binning, datalog, SPC |
| eFuse / OTP (permanent trim) | Bandgap, temperature-sensor offset, detector offset and slope, VCO band, IF filter R/C codes, LO/PA bias | Wafer or final test, once | Compute → burn → re-measure to verify |
| Module flash (calibration tables) | Rx/Tx gain and phase vectors, phase-rotator LUT, Tx power vs temperature, I/Q coefficients | Module EOL (with the real antenna) | Host MCU stores; loaded at boot |
| Runtime (closed loop) | Tx power servo (how the loop works), temperature recalibration, safety monitor reports | Every frame or every N frames | RF ctrl CPU → registers; faults → error pin / host |
Order matters. Trim the references first (bandgap → aux ADC → temperature sensor → power detector). Every later measurement depends on them, so a wrong bandgap trim makes every downstream result wrong in the same way.
07
Production flow on a low-cost tester
- Contact and DC: continuity, leakage, IDDQ, supply currents (ATE PMU). See open/short & Cres test.
- Digital: scan / ATPG, logic BIST, memory BIST (with repair if available), eFuse read. Details, including stress screening, on the digital DFT page.
- Boot test firmware over SPI into the RF control CPU's RAM; the ATE supplies the 40 MHz reference.
- Reference trims: bandgap and aux ADC (compare against one precision ATE voltage), temperature sensor (against the chuck or handler temperature).
- LO: VCO band calibration, lock, counter check of band edges, chirp linearity.
- Tx (A): power per Tx and gain code; reverse-power check with the load-board termination.
- Loopback (B, C, E): run all Rx in parallel: gain, phase, I/Q, NF, IF response, ADC SNR/SFDR, then the phase-rotator sweep.
- Burn eFuse, re-run a short verify subset, read the final result block. Bin.
- Hot/cold insertion: re-run the short list at temperature to fill the temperature LUT and catch drift outliers.
Where the test time goes
- Most BIST measurements take µs to a few ms: one chirp capture plus an FFT.
- All Rx measured at once; the Tx measured by switching, not by moving an instrument.
- No instrument settling, RF switch matrix or GPIB/LAN transfers; only a short SPI readout of results.
- Multi-site becomes easy: 8–32 sites need only digital pins, DC and a shared reference clock.
- The rest is fixed overhead: FW download, eFuse burn, temperature soak. Compress the FW and burn eFuses on all sites in parallel.
Load board without RF instruments
- Terminate each Tx ball in a matched load, which gives a known reflection for the reverse-detector test.
- Optionally, a passive external loopback: a Tx ball → attenuator/trace → Rx ball on the load board. This also tests the balls, bumps and package transitions, which the on-chip loopback cannot see.
- A longer trace gives a real delay τ, so a chirp produces f_b = S·τ; it checks slope end-to-end.
- Keep one audit RF tester for sample-based correlation, not for every part.
08
Accuracy, correlation and coverage limits
BIST measures relative quantities very well (channel matching, steps, linearity, trends). Absolute quantities (Pout in dBm, NF in dB) inherit the uncertainty of an on-chip reference, such as the coupler, detector or noise-source ENR, which varies with process.
| Quantity | Typical BIST accuracy | Main error source | How to handle it |
|---|---|---|---|
| Rx/Tx relative gain | ±0.1–0.2 dB | Coupler asymmetry between channels | Symmetric layout; one-time characterisation |
| Rx/Tx relative phase | ±1–2° | Loopback routing length mismatch | Matched routing; correction constants from design |
| Absolute Tx power | ±0.5–1 dB | Detector slope and coupling spread | Detector trim; golden-unit correlation |
| Noise figure | ±0.7–1.5 dB | Absolute gain or ENR uncertainty | Correlation + guard band; audit sampling |
| LO frequency | ≤ ref ppm + 1/T_gate | Crystal accuracy | Use the ATE's precision reference during test |
Correlation and guard-banding
1. Characterise N_golden ≥ 30 units per lot corner on full RF ATE / bench
2. Fit true = a · BIST + b (per test, per channel), record residual σ
3. Test limit = spec limit ∓ (k·σ_residual), k ≈ 3
4. Ongoing: audit sample per lot on the RF tester; alarm on drift of b
What the loopback cannot see
- Package and balls beyond the couplers: use the reverse detector against the load-board termination, or the passive external loopback.
- Faults in the test circuitry itself: a broken loopback or a detector stuck at a plausible value. Add self-checks: loopback on vs off, detector with PA off must read offset only, both bandgaps must agree.
- Common-mode faults: a shared LO fault affects the stimulus and the receiver equally and can cancel out in a ratio. Use the counter (D) as an independent check.
- Spurious emission and absolute phase noise far from the carrier: cover them by design and characterisation, plus the PLL monitor. Measuring them in production would still need an instrument.
- Antenna, radome, EIRP: tested at module EOL in a chamber, not at chip level.
09
DFT design checklist
RF / analog
- Couplers weak enough: ≤ 0.1 dB Pout loss, ≤ 0.3 dB NF penalty
- Loopback isolation when off > 60 dB (leakage lands at DC, but its harmonics may not)
- Loopback attenuator range ≥ 30 dB to test from small signal to compression
- Modulator f_m derived from the reference, bin-aligned to the ADC FFT
- Detectors at matched positions on every Tx, with forward and reverse ports
- Two independent bandgaps; aux ADC reference ≠ monitored reference
- Noise source with stable ENR, or design for the cold method
Digital / firmware
- Capture buffer for raw ADC samples of all Rx at once (≥ 1 chirp)
- FFT accelerator reachable from the RF control CPU during test
- PLL phase-error and counter readable at high rate
- Test FW loadable over SPI, with limits and results in a compact table
- eFuse burn + verify built into the FW; lockout after programming
- Same monitor code reused in the field for the ISO 26262 safety mechanisms
- Datalog format that includes the raw values, not just pass/fail, for correlation
10
Glossary of abbreviations
Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.
Radar system & ADAS
| Abbr. | Stands for | Note |
|---|---|---|
| FCW | Forward Collision Warning | Warns of an imminent frontal collision; stage before AEB. |
| FCTA | Front Cross-Traffic Alert | Front corner-radar function at junctions and driveways. |
| RCTB | Rear Cross-Traffic Braking | Brakes automatically when RCTA detects cross traffic while reversing. |
| DOW | Door-Opening Warning | Warns before a door is opened into an approaching cyclist or car. |
| VRU | Vulnerable Road User | Pedestrians, cyclists and motorcyclists. |
| TTC | Time To Collision | Range divided by closing speed; triggers warnings and braking. |
| LRR | Long-Range Radar | Front radar, ≈ 200–300 m, narrow field of view. |
| MRR | Mid-Range Radar | ≈ 80–160 m, ±40–60° field of view. |
| SRR | Short-Range Radar | Corner radar, ≈ 30–80 m, ±75–90° field of view. |
| NCAP | New Car Assessment Programme | Consumer safety ratings (Euro NCAP, C-NCAP, IIHS …). |
| GSR | General Safety Regulation (EU) 2019/2144 | Makes AEB and other assistance functions mandatory in the EU. |
| CPD | Child Presence Detection | In-cabin sensing (often 60 GHz radar) that detects a child left in the car. |
| ACC | Adaptive Cruise Control | Keeps distance to the car ahead; uses long-range front radar. |
| ADAS | Advanced Driver-Assistance Systems | The vehicle functions the radar serves. |
| AEB | Autonomous Emergency Braking | Brakes automatically when a collision is imminent. |
| BSD | Blind-Spot Detection | Corner-radar function. |
| LCA | Lane-Change Assist | Corner-radar function that warns of fast approaching vehicles. |
| RCTA | Rear Cross-Traffic Alert | Rear corner-radar function when reversing. |
| L2 | SAE automation Level 2 (L3 = Level 3) | Partial (L2) and conditional (L3) driving automation. |
| FMCW | Frequency-Modulated Continuous Wave | A linear chirp; range comes from the beat frequency f_b = S·2R/c. |
| FoV | Field of View | Angular coverage in azimuth and elevation. |
| RCS | Radar Cross Section | Target reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0). |
| dBsm | Decibels relative to 1 m² | Unit of RCS. |
| EIRP | Effective Isotropic Radiated Power | Tx power + antenna gain; limited by regulations. |
| MIMO | Multiple-Input Multiple-Output | N_tx × N_rx channels form a larger virtual array. |
| TDM | Time-Division Multiplexing | One Tx per chirp; v_max falls by a factor of N_tx. |
| BPM | Binary Phase Modulation | 0/180° codes across chirps separate the Tx signals. |
| DDMA | Doppler-Division Multiple Access | Each Tx gets a slow-time phase ramp and separates in Doppler. |
| DoA | Direction of Arrival | Angle estimation over the virtual array. |
| DBF | Digital Beamforming | FFT or matched steering over array channels. |
| CFAR | Constant False Alarm Rate | Adaptive detection threshold (CA = cell-averaging, OS = ordered-statistic). |
| FFT | Fast Fourier Transform | Range, Doppler and angle FFTs build the radar cube. |
| SNR | Signal-to-Noise Ratio | |
| MUSIC | MUltiple SIgnal Classification | Subspace super-resolution DoA algorithm. |
| ESPRIT | Estimation of Signal Parameters via Rotational Invariance Techniques | Super-resolution DoA algorithm. |
| IAA | Iterative Adaptive Approach | Super-resolution spectral / DoA estimator. |
| DBSCAN | Density-Based Spatial Clustering of Applications with Noise | Groups detections into objects. |
| EKF | Extended Kalman Filter | Nonlinear tracking filter. |
| UKF | Unscented Kalman Filter | Nonlinear tracking filter using sigma points. |
| IMM | Interacting Multiple Model | Tracker that mixes several motion models. |
| HWA | Hardware Accelerator | On-chip FFT / radar processing engine. |
| RTS | Radar Target Simulator | Echo generator for HIL and EOL testing. |
| HIL | Hardware-in-the-Loop | Testing the real sensor against simulated scenarios. |
| EOL | End-of-Line | Final production test of a module or vehicle. |
RF & analog front end
| Abbr. | Stands for | Note |
|---|---|---|
| HPBW | Half-Power Beamwidth | Angle between the −3 dB points of an antenna or array beam. |
| PDN | Power Delivery Network | Regulators, planes, decoupling and package paths that supply the chip. |
| PI | Power Integrity | Keeping supply voltage within limits under load steps and noise. |
| EMI | Electromagnetic Interference | Unwanted emission or pick-up of electromagnetic energy. |
| BCI | Bulk Current Injection | Immunity test (ISO 11452-4) that injects RF current into a cable harness. |
| TIM | Thermal Interface Material | Gap pad or paste between board or package and the heat sink. |
| RF | Radio Frequency | Here the 76–81 GHz signal. |
| LO | Local Oscillator | The chirp signal that drives the Tx and the Rx mixers. |
| IF | Intermediate Frequency | The beat / baseband signal after the mixer, DC–20 MHz. |
| PA | Power Amplifier | Tx output stage, 12–14 dBm. |
| LNA | Low-Noise Amplifier | First Rx stage; sets most of the NF. |
| NF | Noise Figure | Noise the receiver adds, in dB. |
| VGA | Variable-Gain Amplifier | Programmable-gain stage (IF), or signed VGAs in the phase rotator. |
| TIA | Transimpedance Amplifier | Current-to-voltage stage after a passive mixer. |
| HPF | High-Pass Filter | In IF: removes leakage and DC, and equalises R⁻⁴. |
| LPF | Low-Pass Filter | |
| AAF | Anti-Aliasing Filter | Low-pass filter in front of the ADC. |
| PPF | Polyphase Filter | RC-CR network that generates I/Q. |
| I/Q | In-phase / Quadrature | Two copies of a signal 90° apart. |
| IRR | Image Rejection Ratio | How well an I/Q path suppresses the mirror frequency. |
| SSB | Single Sideband | A frequency shift in one direction only, e.g. the loopback offset. |
| BPSK | Binary Phase-Shift Keying | 0/180° switching; produces ±f_m sidebands. |
| VM | Vector Modulator | I/Q-weighted phase rotator. |
| RTPS | Reflection-Type Phase Shifter | Hybrid coupler terminated by tunable loads. |
| P1dB | 1 dB compression point | Input (or output) level where gain drops by 1 dB. |
| IIP3 | Input third-order intercept point | Linearity figure; cascades with the gain before each stage. |
| PAE | Power-Added Efficiency | (P_out − P_in) / P_DC of a PA. |
| Psat | Saturated output power | Maximum output power of a PA. |
| DSB | Double Sideband | Noise figure counting both sidebands (typical for zero-IF mixers). |
| PGA | Programmable-Gain Amplifier | IF VGA with digitally set gain steps. |
| AGC | Automatic Gain Control | Loop that sets the VGA gain from the signal level. |
| HD2 | 2nd-order Harmonic Distortion (HD3 = 3rd) | Harmonics show up as ghost targets at 2×/3× range. |
| AM/PM | Amplitude-to-phase conversion | Phase change caused by amplitude or supply changes. |
| RL | Return Loss | Match quality, in dB. |
| Cpl | Coupler (directional coupler) | Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback. |
| PD | Power Detector | Diode or square-law RF-to-DC converter. |
| APC | Automatic Power Control | Closed loop from the power detector to the VGA/PA gain code. |
| DPD | Digital Predistortion | Wideband PA linearisation used in comms; radar uses static gain/phase LUTs instead. |
| VSWR | Voltage Standing-Wave Ratio | Mismatch at the antenna/load; changes the delivered power. |
| CW | Continuous Wave | An unmodulated single-frequency tone. |
| ENR | Excess Noise Ratio | Calibrated output level of a noise source. |
| SiGe | Silicon-Germanium (BiCMOS) | Bipolar-plus-CMOS process used for earlier radar chips. |
| CMOS | Complementary Metal-Oxide-Semiconductor | RFCMOS = CMOS process with RF / mmWave capability. |
| RFCMOS | RF-capable CMOS | Today's single-chip radar process (e.g. 45/40/28/22 nm). |
| NMOS | N-channel MOS transistor (PMOS = P-channel) | |
| PTAT | Proportional To Absolute Temperature | Voltage or current used by temperature sensors. |
| BG | Bandgap reference | Temperature-stable voltage reference (BG1/BG2 = two independent ones). |
| PVT | Process, Voltage, Temperature | Variation corners a design must cover. |
LO, clock & synthesis
| Abbr. | Stands for | Note |
|---|---|---|
| PLL | Phase-Locked Loop | Locks the VCO to the crystal and generates the ramp. |
| ADPLL | All-Digital PLL | PLL with a TDC and a digital loop filter. |
| VCO | Voltage-Controlled Oscillator | ≈ 19–20.25 GHz, multiplied ×4 to 77 GHz. |
| PFD | Phase-Frequency Detector | Compares the divided VCO with the reference. |
| CP | Charge Pump; also Chip Probe | In a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test. |
| TDC | Time-to-Digital Converter | Digital phase detector of an ADPLL. |
| XTAL | Crystal (reference oscillator) | 40/50 MHz reference for PLL, ADC and digital. |
| DDS | Direct Digital Synthesizer | Digitally generated tone (IF test tone). |
| Kvco | VCO gain | Tuning sensitivity in MHz/V; varies per band. |
| AFC | Automatic Frequency Calibration (band calibration) | Picks the VCO capacitor-bank band before the PLL closes. |
| MMD | Multi-Modulus Divider | Programmable divider in the PLL feedback, dithered by the ΣΔ modulator. |
| CML | Current-Mode Logic | Fast differential logic used for the first divider (prescaler) stages at 20 GHz. |
Data conversion & digital
| Abbr. | Stands for | Note |
|---|---|---|
| SNM | Static Noise Margin | Noise an SRAM cell tolerates before flipping; read SNM is the critical one. |
| SEU | Single-Event Upset | Bit flip caused by a particle strike (soft error). |
| SER | Soft-Error Rate | Rate of radiation-induced bit flips, in FIT per Mbit. |
| MBU | Multi-Bit Upset | One particle flips several neighbouring cells. |
| RDF | Random Dopant Fluctuation | Random number of dopant atoms in a small channel; main cause of Vth mismatch. |
| LER | Line-Edge Roughness | Rough gate edges that add Vth variation in small devices. |
| NPSF | Neighbourhood Pattern-Sensitive Fault | Memory cell fails only for certain data in its neighbours. |
| SEC-DED | Single-Error Correction, Double-Error Detection | ECC code used on memory words (e.g. 64 + 8 bits). |
| ROM | Read-Only Memory | Mask-programmed memory for boot code and tables. |
| DRF | Data-Retention Fault | Memory cell loses its value after a pause. |
| WL | Word Line | Row select line of a memory array. |
| BL | Bit Line | Column data line of a memory array (BL and its complement BLB). |
| OSR | Oversampling Ratio | fs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR. |
| NTF | Noise Transfer Function | How a ΣΔ loop shapes quantisation noise out of the signal band. |
| SNDR | Signal-to-Noise-and-Distortion Ratio | ENOB = (SNDR − 1.76) / 6.02. |
| GBW | Gain-Bandwidth product | Op-amp figure of merit; sets filter and PGA accuracy at IF. |
| CMRR | Common-Mode Rejection Ratio | How well a differential circuit rejects signals common to both inputs. |
| CSI-2 | MIPI Camera Serial Interface 2 | High-speed serial link used for raw radar data. |
| TSN | Time-Sensitive Networking | Deterministic automotive Ethernet (IEEE 802.1). |
| ADC | Analog-to-Digital Converter | Main Rx ADCs (ΣΔ) and the aux SAR ADC. |
| DAC | Digital-to-Analog Converter | Rotator I/Q weights, bias, trim, test-tone generation. |
| SAR | Successive-Approximation Register ADC | Slow, precise ADC used for monitoring. |
| CT | Continuous-Time (CT-ΣΔ) | Sigma-delta ADC with a continuous-time loop filter. |
| ENOB | Effective Number of Bits | |
| SFDR | Spurious-Free Dynamic Range | Tone relative to the largest spur. |
| THD | Total Harmonic Distortion | |
| DR | Dynamic Range | |
| INL | Integral Nonlinearity | Deviation from the ideal transfer line. |
| DNL | Differential Nonlinearity | Deviation of each step from 1 LSB. |
| LSB | Least Significant Bit (MSB = most significant) | |
| DFE | Digital Front End | Decimation, DC and I/Q correction, interference handling. |
| CIC | Cascaded Integrator-Comb | Multiplier-free decimation filter. |
| FIR | Finite Impulse Response filter | |
| DSP | Digital Signal Processor | |
| MCU | Microcontroller Unit | |
| CPU | Central Processing Unit | E.g. the RF control CPU that runs chirps and monitors. |
| SoC | System-on-Chip | |
| ECU | Electronic Control Unit | Vehicle computer that receives radar data. |
| SRAM | Static RAM (RAM = random-access memory) | |
| ECC | Error-Correcting Code | Memory protection for functional safety. |
| DMA | Direct Memory Access | |
| LUT | Look-Up Table | E.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature. |
| FW | Firmware (SW = software) | |
| OTP | One-Time Programmable memory | Holds trims and IDs, like eFuse. |
| SPI | Serial Peripheral Interface | Configuration / test bus from host or ATE. |
| CAN | Controller Area Network (CAN-FD = Flexible Data-rate) | Vehicle bus for object lists. |
| ETH | Ethernet (100/1000BASE-T1) | Automotive single-pair Ethernet. |
| CSI | Camera Serial Interface (MIPI CSI-2) | Streams raw radar data to a central SoC. |
| LVDS | Low-Voltage Differential Signaling | Raw-data debug / streaming interface. |
| GPIO | General-Purpose Input/Output | |
| IO | Input/Output |
Power
| Abbr. | Stands for | Note |
|---|---|---|
| LDO | Low-Dropout regulator | Linear regulator; one per noise-sensitive domain. |
| PMIC | Power-Management IC | External bucks, supervisors and watchdog. |
| PSRR | Power-Supply Rejection Ratio | How much supply ripple an LDO (or circuit) blocks. |
| UV | Under-Voltage (OV = Over-Voltage) | Supply monitors, a safety mechanism. |
| OV | Over-Voltage | Rail above its window; OV monitor protects gate oxides. |
| POR | Power-On Reset | Holds the chip in reset until all rails are valid. |
| BOR | Brown-Out Reset | Resets when a supply sags during operation. |
| ESR | Equivalent Series Resistance | Of the LDO output capacitor; its zero affects loop stability. |
| OCP | Over-Current Protection | Current limit on a regulator output. |
| Iq | Quiescent current | Current a regulator draws for itself with no load. |
| DLDO | Digital LDO | Switched pass-device array regulated by a comparator loop. |
| GND | Ground |
Test & production
| Abbr. | Stands for | Note |
|---|---|---|
| EVB | Evaluation Board | Board that carries the chip on the bench with supplies, clock, interfaces and RF transitions. |
| SMU | Source-Measure Unit | Precision instrument that forces voltage or current and measures the other. |
| OTA | Over The Air | Measurement through antennas in a chamber instead of a cable or waveguide. |
| GSG | Ground-Signal-Ground probe | RF wafer probe with a signal tip between two ground tips. |
| LRRM | Line-Reflect-Reflect-Match calibration | On-wafer VNA calibration method for mmWave probes. |
| SCPI | Standard Commands for Programmable Instruments | Text command set used to automate instruments. |
| UPH | Units Per Hour | Test throughput of a tester and handler. |
| eFuse | Electrically programmable fuse | Silicided poly link blown by current; stores trim, ID and repair bits. |
| MTP | Multiple-Time Programmable memory | Small NVM that can be rewritten a few times. |
| NVM | Non-Volatile Memory | Keeps data without power: eFuse, OTP, MTP, flash. |
| VPP | Programming supply voltage | Supply used only to program fuses or OTP. |
| CRC | Cyclic Redundancy Check | Checksum that detects corrupted data, e.g. trim words at boot. |
| RMA | Return Material Authorization | A customer return, analysed through the 8D process. |
| 8D | Eight Disciplines | Structured problem solving: team, describe, contain, root cause, correct, verify, prevent, close. |
| MSA | Measurement System Analysis | Proves a measurement is precise and accurate enough (Gage R&R, bias, stability). |
| GRR | Gage Repeatability and Reproducibility | %GRR < 10 % of tolerance is good. |
| BIST | Built-In Self-Test | On-chip stimulus + measurement; result is pass/fail or a value checked against a limit. |
| BISM | Built-In Self-Measurement | Same on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend. |
| DFT | Design for Test | |
| ATE | Automatic Test Equipment | Production tester. |
| ATPG | Automatic Test Pattern Generation | Scan patterns for digital logic. |
| IDDQ | Quiescent supply-current test | Detects leakage defects. |
| PMU | Parametric Measurement Unit | ATE DC source/measure channel. |
| Cres | Contact resistance | Probe or socket contact resistance; measured with the Kelvin or two-current method. |
| FIMV | Force Current, Measure Voltage | PMU mode used for open/short (diode) tests. |
| FVMI | Force Voltage, Measure Current | PMU mode used for leakage and power-short tests. |
| IIL | Input leakage current, input Low (IIH = input High) | Leakage limit per IO pin, typically |I| < 1 µA. |
| IIH | Input leakage current, input High | |
| ESD | Electrostatic Discharge | Pad protection diodes / clamps; the diode method uses them for continuity. |
| VDD | Positive supply rail (VSS = ground / negative rail) | |
| VSS | Ground / negative supply rail | |
| DCR | DC Resistance | E.g. of an RF shunt inductor, 0.5–3 Ω. |
| Hi-Z | High impedance (Z) | Output driver switched off; the pin floats. |
| OE | Output Enable | Control that switches an output between driving and Hi-Z. |
| IOZ | Off-state output leakage (IOZH at VDDIO, IOZL at 0 V) | Measured on a pin in Hi-Z; typically |I| < 1–10 µA. |
| VOH | Output High voltage threshold (VOL = Output Low) | Tester comparator levels that decide 1 / Z / 0. |
| VOL | Output Low voltage threshold | |
| HIGHZ | IEEE 1149.1 instruction that puts all outputs in Hi-Z | |
| EXTEST | IEEE 1149.1 external test instruction | Boundary cells drive and sample the pins; used for interconnect and walking-Z tests. |
| RPCT | Reduced Pin-Count Testing | Testing through JTAG / a few pins, so more sites fit on one tester. |
| BICS | Built-In Current Sensor | On-chip current monitor for IDDQ per power domain. |
| SPC | Statistical Process Control | |
| VNA | Vector Network Analyzer | Lab instrument for S-parameters. |
| AWG | Arbitrary Waveform Generator | |
| DMM | Digital Multimeter | |
| GPIB | General-Purpose Interface Bus | Instrument control bus (like LAN). |
Safety, standards & regulation
| Abbr. | Stands for | Note |
|---|---|---|
| PMHF | Probabilistic Metric for random Hardware Failures | ISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D. |
| SEooC | Safety Element out of Context | A part developed to ISO 26262 against assumed system requirements. |
| FMEA | Failure Mode and Effects Analysis | Qualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage. |
| FIT | Failures In Time | Failures per 10⁹ device-hours. |
| MTTF | Mean Time To Failure | |
| RED | Radio Equipment Directive (EU 2014/53/EU) | EU conformity framework for radio transmitters, including radar. |
| ASIL | Automotive Safety Integrity Level | ISO 26262 risk class A–D; radar typically ASIL-B. |
| ISO | ISO 26262 / ISO/SAE 21434 / ISO 11452 | Functional safety / cybersecurity / EMC immunity. |
| FTTI | Fault-Tolerant Time Interval | Time from fault to hazard; monitors must react within it. |
| FMEDA | Failure Modes, Effects and Diagnostic Analysis | |
| SPFM | Single-Point Fault Metric | ISO 26262 coverage metric. |
| LFM | Latent Fault Metric | ISO 26262 coverage metric. |
| AEC | Automotive Electronics Council (AEC-Q100 / Q200) | Qualification of ICs / passives. |
| ETSI | European Telecommunications Standards Institute | EN 301 091 / EN 303 396 radar standards. |
| FCC | Federal Communications Commission | US rules, Part 95M for 76–81 GHz. |
| EMC | Electromagnetic Compatibility | |
| CISPR | Comité International Spécial des Perturbations Radioélectriques | CISPR 25: vehicle-component emissions. |
| OOB | Out-of-Band (emission) |
Digital DFT, stress & reliability
| Abbr. | Stands for | Note |
|---|---|---|
| UHST | Unbiased Highly Accelerated Stress Test | HAST without bias, 130 °C / 85 % RH; alternative to autoclave. |
| PTC | Power Temperature Cycling | Temperature cycling with the device powered on and off. |
| EDR | Endurance and Data Retention | Qualification of non-volatile memory (AEC-Q100-005). |
| DPA | Destructive Physical Analysis | Opening and sectioning parts to inspect their construction and damage. |
| SEM | Scanning Electron Microscope | High-magnification imaging of cross-sections and surfaces. |
| EDX | Energy-Dispersive X-ray spectroscopy | Element analysis in the SEM: corrosion, contamination, IMC phases. |
| FIB | Focused Ion Beam | Precise local cutting and imaging; also used for circuit edits. |
| LTPD | Lot Tolerance Percent Defective | Defect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %. |
| PC | Preconditioning | Bake, moisture soak and reflow before environmental stress (JESD22-A113). |
| BLR | Board-Level Reliability | Reliability of the package soldered on a PCB (temperature cycling, drop, vibration). |
| SAC | Tin-Silver-Copper solder | Lead-free solder alloy (e.g. SAC305) used for balls. |
| PPAP | Production Part Approval Process | Automotive approval package, includes the qualification report. |
| DRC | Design Rule Check | Verifies layout against foundry manufacturing rules. |
| LVS | Layout Versus Schematic | Verifies that the layout matches the schematic netlist. |
| PEX | Parasitic Extraction | Extracts resistance, capacitance (and inductance) of the layout for post-layout simulation. |
| AMS | Analog / Mixed-Signal simulation | Simulation that combines transistor-level analog with digital models. |
| ECO | Engineering Change Order | Late design fix; a metal-only ECO changes only upper masks. |
| SCR | Silicon-Controlled Rectifier | Thyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up. |
| GGNMOS | Grounded-Gate NMOS | ESD clamp that works by parasitic-bipolar snapback. |
| SE | Scan Enable | Selects shift (SE = 1) or functional capture (SE = 0) in scan flops. |
| SAF | Stuck-At Fault | Node permanently 0 or 1. |
| TDF | Transition Delay Fault | Node slow to rise or fall; needs at-speed test. |
| STA | Static Timing Analysis | Finds the longest paths for timing-aware ATPG. |
| OCV | On-Chip Variation | Timing derates in STA that account for local (mismatch) variation across the die. |
| OCC | On-Chip Clock Controller | Gates exact launch/capture pulses from the PLL for at-speed test. |
| LOC | Launch-On-Capture | At-speed scheme; also called broadside. |
| LOS | Launch-On-Shift | At-speed scheme; SE must switch at speed. |
| EDT | Embedded Deterministic Test | Scan compression (decompressor + compactor). |
| LFSR | Linear-Feedback Shift Register | Pseudo-random sequence generator. |
| PRPG | Pseudo-Random Pattern Generator | LFSR that feeds the scan chains in LBIST. |
| MISR | Multiple-Input Signature Register | Compresses responses into one signature. |
| STUMPS | Self-Test Using MISR and Parallel Shift-register sequence generator | Standard LBIST architecture. |
| LBIST | Logic BIST | On-chip random-pattern scan test; used at key-on. |
| MBIST | Memory BIST | On-chip March-algorithm test of SRAMs. |
| BIRA | Built-In Redundancy Analysis | Computes which spare rows/columns repair a memory. |
| BISR | Built-In Self-Repair | Loads the repair from eFuse at boot. |
| IR | IR drop | Supply voltage drop (current × resistance), high during scan shift. |
| JTAG | Joint Test Action Group (IEEE 1149.1) | Boundary scan and test access port. |
| TAP | Test Access Port | JTAG pins TCK, TMS, TDI, TDO, TRST. |
| BSDL | Boundary Scan Description Language | Describes a chip's JTAG boundary-scan cells. |
| IJTAG | Internal JTAG (IEEE 1687) | Network for accessing on-chip instruments. |
| MUX | Multiplexer | Selects one of N inputs; in test, routes sub-block nodes to shared instruments. |
| ATB | Analog Test Bus | Chip-wide wire pair (force + sense) that test muxes connect sub-block nodes to. |
| TG | Transmission Gate | Parallel NMOS + PMOS switch; passes the full voltage range. |
| SPDT | Single-Pole Double-Throw switch | One input to one of two outputs (SP4T = one of four). |
| BBM | Break-Before-Make | Switching order that opens the old path before closing the new one. |
| ICL | Instrument Connectivity Language (PDL = Procedural Description Language) | IJTAG description files. |
| ECID | Electronic Chip ID | Unique per-die ID for traceability. |
| HVST | High-Voltage Stress Test | Short over-voltage on the core rail to activate latent oxide defects. |
| VLV | Very-Low-Voltage test | Test below nominal V to expose resistive defects. |
| Vmin | Minimum operating voltage | The pass/fail edge in a shmoo; an outlier Vmin flags a defect. |
| PAT | Part Average Testing (AEC-Q001) | Outlier limits at robust μ ± 6σ. |
| DPAT | Dynamic Part Average Testing | PAT limits recalculated per lot or wafer. |
| GDBN | Good Die in Bad Neighbourhood | Wafer-map screen that rejects dies in defect clusters. |
| NNR | Nearest-Neighbour Residual | Compares a die's parameter with its wafer neighbours. |
| DPPM | Defective Parts Per Million | Shipped-quality metric; automotive target ≪ 1. |
| FT | Final Test | Package-level production test. |
| SLT | System-Level Test | Functional test by booting the application. |
| PCM | Process Control Monitor | Test structures in the scribe lines, measured by the fab (see WAT). |
| WAT | Wafer Acceptance Test | Fab's electrical test of PCM structures before shipping wafers. |
| OSAT | Outsourced Semiconductor Assembly and Test | Company that packages and tests the dies. |
| QA | Quality Assurance | Sample-based outgoing inspection and audits. |
| Cp | Process capability (Cp) | (USL − LSL) / 6σ: spec width vs process spread. |
| Cpk | Process capability index | min(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67. |
| USL | Upper Spec Limit (LSL = Lower Spec Limit) | Design limits; outside them the part is out of spec. |
| LSL | Lower Spec Limit | |
| UCL | Upper Control Limit (LCL = Lower Control Limit) | Process limits from history, usually mean ± 3σ. |
| LCL | Lower Control Limit | |
| OCAP | Out-of-Control Action Plan | Documented steps when an SPC rule fires. |
| MRB | Material Review Board | Decides what happens to held material: release, rework, scrap or deviation. |
| MIM | Metal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal) | Precision on-chip capacitors. |
| MOM | Metal-Oxide-Metal (finger) capacitor | |
| BSIM | Berkeley Short-channel IGFET Model | Industry-standard compact transistor model family used in design kits. |
| Vt | Threshold voltage | Gate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD. |
| Idsat | Saturation drain current | Id at Vgs = Vds = VDD, per µm of width; transistor strength. |
| Ioff | Off-state leakage current | Id at Vgs = 0, Vds = VDD. |
| DIBL | Drain-Induced Barrier Lowering | Vt drop per volt of Vds in short-channel devices. |
| SS | Subthreshold swing (also SS = slow-slow process corner) | mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature. |
| TT | Typical-typical process corner | FF = fast-fast; FS / SF = skewed NMOS / PMOS corners. |
| FF | Fast-fast process corner | |
| gm | Transconductance | ∂Id/∂Vgs; the transistor's gain. |
| gds | Output conductance | ∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds). |
| Cox | Gate-oxide capacitance per area | εox / Tox. |
| Tox | Gate-oxide thickness | Measured with C-V structures in WAT. |
| fT | Transit (unity current-gain) frequency | ≈ gm / 2π(Cgs + Cgd). |
| fmax | Maximum oscillation (unity power-gain) frequency | Needs ≈ 3–4× the operating frequency for useful gain. |
| Vbd | Gate-oxide breakdown voltage | Voltage where oxide current jumps past compliance in a V-ramp test. |
| BV | Breakdown Voltage | BVdss = drain-source (gate off), BVj = junction. |
| BVdss | Drain-source breakdown voltage | Transistor off-state breakdown; limits PA drain swing. |
| BVj | Junction breakdown voltage | Reverse breakdown of N+/P-well or P+/N-well diodes. |
| TLP | Transmission-Line Pulse | ESD device characterisation with short, high-current pulses. |
| QBD | Charge to breakdown | Total charge an oxide passes before breaking down (reliability). |
| IMD | Inter-Metal Dielectric | Insulator between metal lines/layers; tested with comb structures. |
| CMP | Chemical-Mechanical Planarization | Polishing step that flattens each layer; source of centre, edge and ring signatures. |
| OPC | Optical Proximity Correction | Mask shape corrections; weak spots (hotspots) can fail per reticle shot. |
| EBR | Edge Bead Removal | Removes resist build-up at the wafer edge. |
| D0 | Defect density | Random defects per unit area; baseline yield Y ≈ e^(−D0·A). |
| HTOL | High-Temperature Operating Life | ≈ 1000 h biased at max temperature (AEC-Q100). |
| ELFR | Early Life Failure Rate | Short high-temperature operation of a large sample. |
| TC | Temperature Cycling | Package and interconnect fatigue test. |
| THB | Temperature-Humidity-Bias | 85 °C / 85% RH with bias. |
| HAST | Highly Accelerated Stress Test | 130 °C / 85% RH with bias. |
| RH | Relative Humidity | |
| HTSL | High-Temperature Storage Life | Unbiased bake. |
| HBM | Human-Body Model (ESD) | |
| CDM | Charged-Device Model (ESD) | |
| LU | Latch-Up | JESD78 test. |
| EM | Electromigration | Metal wear-out under current (wafer-level reliability). |
| TDDB | Time-Dependent Dielectric Breakdown | Gate-oxide wear-out. |
| HCI | Hot-Carrier Injection | Transistor degradation mechanism. |
| NBTI | Negative-Bias Temperature Instability | PMOS threshold drift. |
PCB, package & materials
| Abbr. | Stands for | Note |
|---|---|---|
| TCB | Thermo-Compression Bonding | Flip-chip attach with heat and force per die; fine pitch, low warpage. |
| MUF | Molded Underfill | Mold compound that also fills the gap under a flip-chip die. |
| CSAM | C-mode Scanning Acoustic Microscopy | Ultrasound imaging of voids and delamination inside packages. |
| AOI | Automated Optical Inspection | Camera inspection of RDL, bumps and balls in the assembly line. |
| KGD | Known-Good Die | Die that passed wafer sort and is released for assembly. |
| WLP | Wafer-Level Package | Package built on the whole wafer (fan-in) or a reconstituted wafer (fan-out). |
| PCB | Printed Circuit Board | |
| RDL | Redistribution Layer | Thin-film Cu wiring that routes die pads to balls (fan-out) or bumps. |
| UBM | Under-Bump Metallisation | Metal stack between die/RDL pad and the solder. |
| FOWLP | Fan-Out Wafer-Level Package | Die embedded in mold with RDL fanning out to balls; eWLB is one type. |
| CSP | Chip-Scale Package | Package only slightly larger than the die (FC-CSP = flip-chip CSP). |
| AiP | Antenna-in-Package | Antennas built into package layers. |
| IMC | Intermetallic Compound | Layer formed between solder and UBM/pad; grows with time and temperature. |
| CTE | Coefficient of Thermal Expansion | Mismatch between materials drives solder and bump fatigue. |
| MSL | Moisture Sensitivity Level | J-STD-020 rating: how long a package may sit out of dry pack before reflow. |
| ELK | Extreme Low-k dielectric | Fragile back-end dielectric in advanced nodes; cracks under bump stress. |
| NSMD | Non-Solder-Mask-Defined pad | PCB pad style that improves solder-joint fatigue life. |
| Dk | Dielectric constant | Sets line impedance and antenna tuning; shifts with moisture. |
| Df | Dissipation factor | Dielectric loss; key for RF loss at 77 GHz. |
| C-SAM | C-mode Scanning Acoustic Microscopy | Non-destructive imaging of delamination and voids. |
| PBO | Polybenzoxazole | Polymer dielectric used in RDL (like polyimide). |
| EOS | Electrical Overstress | Damage from overvoltage or overcurrent beyond ESD events. |
| BGA | Ball Grid Array | FC-BGA = flip-chip BGA. |
| eWLB | embedded Wafer-Level Ball-grid-array | Fan-out package with low RF loss. |
| AoP | Antenna-on-Package | |
| LoP | Launch-on-Package | RF launched from package into waveguide / antenna. |
| GCPW | Grounded Coplanar Waveguide | PCB transmission line at the ball launch. |
| SIW | Substrate-Integrated Waveguide | Waveguide formed with via fences in the PCB. |
| FR4 | Flame-Retardant epoxy-glass laminate | Standard low-cost PCB material. |
| ENEPIG | Electroless Nickel, Electroless Palladium, Immersion Gold | PCB surface finish. |
| ImAg | Immersion Silver | PCB surface finish. |
| HASL | Hot-Air Solder Leveling | Surface finish; too rough/uneven for 77 GHz. |
| PBT | Polybutylene terephthalate (PC = polycarbonate) | Radome plastics. |
| HFSS | High-Frequency Structure Simulator (Ansys) | 3D EM simulator (CST = Dassault's equivalent). |