Radar SoC Digital DFT

Why digital DFT matters in a radar SoC

Digital

Without test structures, a digital core with millions of flip-flops can't be tested in reasonable time: functional patterns reach only a small part of the internal states. Design for Test (DFT) adds controllability (set any internal state) and observability (read any internal state). Automatic pattern generation can then target every modelled fault.

Driver	What it means for DFT
Automotive quality target	"Zero defect" culture: field returns well below 1 DPPM. This needs very high fault coverage on several fault models, not just stuck-at.
Large digital content	DSP + HWA + lockstep R5F + 2–8 MB SRAM (single chip), far more on imaging SoCs. Scan data volume and test time dominate unless compressed.
ISO 26262 (ASIL-B)	Latent faults in safety mechanisms must be detected in the field, so logic and memory BIST run at key-on (and sometimes periodically).
Mixed-signal chip	Scan must not disturb the analog/RF blocks, and high toggle activity during shift must not collapse the on-chip supplies.
Cost	Test time × tester cost per second is a large share of unit cost. Compression, multi-site and parallel BIST cut it.

Typical coverage targets (automotive)

Fault model	Typical target	Notes
Stuck-at	≥ 99%	Baseline; automotive customers often require it
Transition (at-speed)	≥ 90–97%	Catches resistive / delay defects that stuck-at misses
Cell-aware	as high as practical	Defects inside standard cells; significantly reduces DPPM at advanced nodes
Memory (March + retention)	≈ 100% of targeted memory faults	Via MBIST, with repair where there is redundancy
In-field LBIST	≈ 90%+ stuck-at of the tested logic	Feeds ISO 26262 latent-fault metric (LFM)

Fault models: what the patterns target

ATPG doesn't look for physical defects directly. It targets abstract fault models that stand in for them. Each model catches a different class of defect, so automotive test combines several.

Model	Assumes	Physical defects covered	Test needs
Stuck-at (SAF)	A node is permanently 0 or 1	Hard opens and shorts to supply	Slow scan, one capture
Transition delay (TDF)	A node is slow to rise or fall	Resistive vias and opens, weak transistors	At-speed launch + capture
Path delay	A whole path exceeds the clock period	Distributed timing degradation	At-speed, specific critical paths
Small delay defect	Small extra delay on a long path	Marginal resistive defects	Timing-aware ATPG, longest paths
Bridging	Two nets shorted (wired-AND/OR or dominant)	Metal shorts between neighbours	Layout-extracted net pairs
Cell-aware	Defect inside a cell's transistor netlist	Intra-cell opens and shorts	Cell library characterisation (SPICE) + ATPG
IDDQ (details)	Defect raises quiescent current	Gate-oxide shorts, bridges	Current measured at static states
Memory faults	Cell stuck-at, transition, coupling, address decoder, retention, neighbourhood pattern	SRAM array defects	March algorithms in MBIST

Scan design, ATPG and test compression

Digital

Every flip-flop is replaced by a scan flip-flop: a D flop with a 2:1 mux in front. When SE (scan enable) = 1 it takes SI from the previous flop, so all flops form a long shift register (a scan chain). When SE = 0 it takes the normal functional input D.

Shift in (SE = 1): clock the pattern into all chains, which sets every flop to a chosen state.
Capture (SE = 0): one or two functional clock pulses. The combinational logic responds and the flops capture its outputs.
Shift out (SE = 1): unload the captured response while loading the next pattern; the tester compares it with the expected values.

ATPG (automatic test pattern generation) computes the patterns from the netlist and the fault models, and reports fault coverage. With millions of flops, uncompressed chains would be millions of cycles long, so every modern SoC uses test compression. A few tester channels feed an on-chip decompressor that drives hundreds of short internal chains, and a compactor folds their outputs back down.

With 100× compression, 8 tester channels drive 800 internal chains. Each chain is about 3 750 flops instead of 375 000, so each pattern needs roughly 100× fewer shift cycles and 100× less tester memory. X-masking blocks unknown values (from memories, analog, uninitialised flops) before they corrupt the compacted response.

Chain length L = N_flops / (N_channels × C) C = compression ratio Test cycles ≈ P × (L + n_capture) + L P = number of patterns Scan time = cycles / f_shift f_shift ≈ 10–100 MHz (power-limited) Data volume ≈ P × L × N_channels × 2 (stimulus + expected response)

Scan design rules

All flops scannable. Exceptions (e.g. asynchronous synchronisers) are documented and handled.
Asynchronous set/reset controllable from a test pin during scan.
No combinational loops; latches transparent or scannable.
Clock gating cells get a test-enable override.
Chains balanced in length and kept within one clock domain, or joined with lockup latches where they cross domains.
Memories and analog wrapped or bypassed so they produce no X values.

Pattern set order

Chain test first (shift a 0011… flush pattern): proves the chains shift before trusting any result.
Stuck-at patterns: the bulk of coverage, run at slow shift.
Transition / at-speed patterns: usually the largest pattern count.
Cell-aware and bridging top-up patterns.
IDDQ vectors: a handful of static states for current measurement.

Muxes in the digital test logic

Most digital DFT is built from 2:1 muxes controlled by test mode: the scan flop is one, and so are the clock, reset and bypass controls around it. Each gives the tester control or observation of something it could not reach in functional mode. The analog and RF test muxes that route sub-blocks to the on-chip instruments are on the BIST page.

Mux	Where	Does	Watch out for
Scan mux (mux-D flop)	In front of every flip-flop	SE selects functional D or scan input SI	Scan-enable is a high-fanout net; it needs its own timing closure for at-speed test
Clock mux / OCC	Root of each clock domain	Switches between the functional PLL clock, the slow tester shift clock and the at-speed pulses	Must be glitch-free (synchronised select); adds insertion delay and skew to the whole domain
Reset and set bypass	Asynchronous reset and set pins of flops	Gives the tester control of reset during shift	Otherwise a reset glitch from logic under test corrupts the chain
Clock-gating test enable	Integrated clock-gating cells	Forces gated clocks on during scan	Without it, flops behind gates are uncontrollable and coverage drops
Memory and analog bypass	Around SRAM, ROM and analog macros	Routes inputs to outputs or to scan flops (wrapper), blocks X values	Unwrapped macros produce X that corrupts compacted results
Pin-sharing (IO) mux	Pad ring	Reuses functional pins as scan-in / scan-out, test clock and test mode	Test functions must be impossible to enable in the field; pad timing differs by mode
Observe / debug mux	Internal status buses	Brings internal signals (lock detect, state machines, clocks ÷N) to a GPIO	Adds load and routing to sensitive nets; disable in mission mode
Test-point mux	Hard-to-control logic cones	Control or observation points inserted for coverage (also for LBIST)	Small area and timing cost; placed by the DFT tool on low-testability nodes

At-speed testing

Digital

Stuck-at testing uses slow clocks, so a defect that only adds delay passes. At-speed tests launch a transition and capture the result one functional clock period later, using the on-chip PLL through an on-chip clock controller (OCC). The tester alone can't deliver two edges hundreds of MHz apart.

Launch-on-capture (LOC, or broadside). SCAN_EN drops during a slow dead time, then the OCC lets exactly two fast PLL pulses through: the first launches transitions from the scanned-in state, the second captures them one functional period later.

Scheme	How the transition is launched	Pros	Cons
Launch-on-capture (LOC)	First functional clock after shift	SE can be slow (no at-speed SE routing); functional-like states	Lower coverage than LOS; more patterns
Launch-on-shift (LOS)	Last shift edge, then SE switches at speed	Higher coverage, fewer patterns	SE must be timed like a clock; may test non-functional paths (over-kill)

Timing-aware ATPG steers transitions through the longest paths (from STA) to catch small delay defects.
Multiple clock domains (CPU, DSP/HWA, ADC interface, SPI): test each domain's intra-domain paths separately; inter-domain paths need controlled clock sequences or are masked.
Over-test risk: at-speed patterns switch more logic at once than any real workload, so IR drop slows the circuit and good parts can fail. Use power-aware ATPG and low-power fill.

IDDQ testing: measuring quiescent current

Digital

In static CMOS, once the inputs stop switching there is no DC path from VDD to VSS: in every gate either the pull-up or the pull-down network is off. The supply current in that quiet state, I_DDQ (I_DD quiescent), is only leakage. Many defects create a real DC path in some logic states, so the current jumps by µA to mA. IDDQ testing loads a state with scan, stops the clocks, and measures that current. It finds defects that voltage-based (logic) tests often miss, because the circuit may still produce correct logic levels.

Why a bridge raises quiescent current. The defect conducts only in vectors that drive the two bridged nodes to opposite values, so IDDQ vectors are chosen to set every node pair both ways. A strong bridge may still resolve to a valid logic level (the stronger driver wins), so a logic test can pass while IDDQ fails.

Defects IDDQ is good at

Defect	Why current flows	Do logic tests see it?
Bridge between nodes at opposite values	VDD → on PMOS → bridge → on NMOS → VSS	Often not, if one driver is much stronger or the bridge is resistive
Gate-oxide short (pinhole)	Gate-to-channel conduction	Usually not: the logic still works, but it is a reliability risk (early-life failure)
Open gate / floating input	The input floats near mid-rail, so both P and N are partly on	Sometimes; timing-dependent
Stuck-on transistor, punch-through	Pull-up and pull-down both conduct	Sometimes
Junction leakage, ESD damage	Leaky diode to the substrate	No

How a measurement is made

Load a state with scan, then stop all clocks.
Switch off everything that draws DC current by design: analog bias, bandgap loads, PLL/VCO, ADC, PA/LNA bias, IO pull-ups/downs, IO drivers in a static state, memories in their lowest-leakage mode. No input may float.
Wait for settling. The decoupling capacitance and supply network must reach DC: t ≈ C·ΔV/I. With µF of decap this is 1–10 ms unless the tester uses a fast range and then switches to a precision meter.
Measure I_DD on the core rail with the tester PMU (nA–mA ranges).
Repeat for N vectors (typically 5–50), chosen by ATPG so that every node is set to both 0 and 1 (toggle / pseudo-stuck-at coverage) and likely bridge pairs are set opposite.

Test time ≈ N_vectors × (scan load + t_settle + t_measure) e.g. 20 × (0.5 + 2 + 1) ms ≈ 70 ms → why IDDQ uses few vectors

The advanced-node problem: leakage hides the defect

At 180 nm a good die drew nA to µA, and a defect added µA to mA, so one fixed limit worked. At 40/28/22 nm, subthreshold and gate leakage from millions of gates give a mA-level baseline that varies several-fold with process corner and rises steeply with temperature (roughly 2× per 10–20 °C). A defect adding tens of µA disappears inside that spread. The fix is to compare each die with itself: across vectors, the leakage baseline stays almost constant and only the defect current switches on and off.

Illustrative example, not measured data. Top: absolute IDDQ per vector (core rail, µA). The defective die sits at a leakier process corner, and its bridge conducts on vectors 4, 9, 13 and 17. It never crosses the fixed 200 µA limit, so it passes. Bottom: ΔIDDQ, the change from the previous vector on the same die. The baseline cancels and the bridge shows as ±38 µA steps outside the ±20 µA limit, so it fails. Hover a point for its value.

Show data as a table

Vector	Good die (µA)	Defective die (µA)	Δ good	Δ defective
1	120	150	—	—
2	123	153	+3	+3
3	118	149	-5	-4
4	121	189 (bridge on)	+3	+40
5	125	152	+4	-37
6	119	150	-6	-2
7	122	148	+3	-2
8	124	154	+2	+6
9	117	189 (bridge on)	-7	+35
10	121	150	+4	-39
11	120	151	-1	+1
12	126	155	+6	+4
13	119	188 (bridge on)	-7	+33
14	123	149	+4	-39
15	118	153	-5	+4
16	122	150	+4	-3
17	125	190 (bridge on)	+3	+40
18	120	152	-5	-38
19	121	148	+1	-4
20	119	151	-2	+3

Screening methods that still work at advanced nodes

Method	Idea	Limit (example)
ΔIDDQ	Vector-to-vector difference on the same die; the leakage baseline cancels	\|I(vᵢ) − I(vᵢ₋₁)\| < 20 µA
Current ratio	Max/min over one die's vectors; independent of that die's leakage corner	I_max / I_min < 1.2 (example: good 1.08, defective 1.30)
Nearest-neighbour residual (NNR)	Predict a die's IDDQ from its wafer neighbours and screen the residual	r = I_die − median(I_neighbours)
Statistical (DPAT)	Outlier limits from the wafer/lot distribution	median ± 6σ (robust)
Temperature / voltage	Test cold to shrink leakage, or compare cold vs hot; reduced VDD	product-specific
Per power domain	Measure gated domains separately, so each baseline is smaller	limit per domain
Pre/post-stress ΔIDDQ	Measure before and after HVST or burn-in; a rise means the stress activated a latent defect	ΔI_stress < limit
Built-in current sensors (BICS)	On-chip current monitors per domain; faster, finer resolution	design-specific

In a radar SoC

Bypass the on-chip LDOs and supply the digital core rail directly from the tester, so the PMU measures only core current (see the power section).
Analog and RF domains off during digital IDDQ. They get their own "static IDD" test with bias on, compared against a characterised range.
SRAM leakage (several MB) is a large part of the baseline, so put memories in retention or lowest-leakage mode, or measure the memory rail separately.
Usually at wafer probe, at room or cold temperature, right after the scan chain test. It pairs well with HVST: IDDQ before and after the stress.

Radar-SoC specifics: scan in a mixed-signal chip

DigitalSupply

Keep the RF and analog safe

During scan, register bits that control analog blocks change at random. Force a safe state through test-mode gating: PA and LO off, VCO disabled, LDOs in a known mode, eFuse programming locked.
Put the analog control registers in wrapper cells that hold their value during shift and are tested by themselves.
An accidental PA enable during scan can exceed EIRP limits on the tester or stress the device.

Shift power vs on-chip LDOs

Random fill makes about 50% of flops toggle every shift cycle. That can be several times the functional current, with a large di/dt.
On-chip LDOs (see the power section) are sized for functional load. Shift current can drop the rail below the retention or timing margin, and good dies fail.
Mitigations: low-power (fill-adjacent) patterns, lower shift frequency, staggered chain clocks, and supplying the core rail from the ATE during scan.

Analog-digital boundaries

ADC outputs are X sources during scan. Mask them, or insert observe/control test points at the digital boundary.
Test the DFE and interfaces with a digital loopback (pattern generator → DFE → capture memory) as well as scan.
Test the ADC, DAC and RF analog content with the BIST/BISM loopbacks on the BIST page.

Clocks for at-speed

The OCC takes the digital PLL clock (not the 20 GHz RF synthesiser) and gates exactly the launch and capture pulses.
The reference crystal comes from the ATE during test, so at-speed frequencies are exact.
Lockstep CPUs: test both cores, and include the comparator logic (a latent-fault target).

Memory BIST and repair

Digital

SRAMs are dense and defect-prone, and they aren't reached efficiently through scan. An on-chip MBIST controller for each memory group generates addresses and data, compares read data, and logs failures. It runs at speed on all memories in parallel (within power limits).

The SRAM itself (bitcell, margins, ECC, redundancy), the full set of memory fault models, Vmin/shmoo testing and how process defects appear in fail bitmaps are on the embedded SRAM page.

March algorithms

March C− (10N operations, N = words) ⇕(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇕(r0) ⇑ ascending address ⇓ descending ⇕ either order Detects: stuck-at, transition, address-decoder, most coupling faults Add: checkerboard / data backgrounds, retention (pause at low V, high T), read-disturb

Item	Radar SoC practice
Memory size	2–8 MB on-chip (radar cube, DSP L2, CPU TCM); MBIST time ∝ N × ops / f
Test time example	1 MB bank as 32-bit words = 262 144 words × 10 ops / 200 MHz ≈ 13 ms per algorithm pass; banks in parallel
Repair	Redundant rows/columns; BIRA computes the repair, the repair word is burned into eFuse and reloaded at boot (BISR)
ECC interaction	Test with ECC bypassed (see the raw array), then test the ECC logic itself (inject single/double-bit errors)
Retention / VLV	Write, wait (ms) at reduced supply and hot, read back: catches weak cells
In-field	Non-destructive or boot-time MBIST as an ISO 26262 latent-fault test for RAM and ECC

Logic BIST and in-field (key-on) test

DigitalISO 26262

Logic BIST reuses the scan chains but replaces the tester with on-chip hardware: an LFSR/PRPG generates pseudo-random patterns, and a MISR compresses all responses into one signature. At the end, the signature is compared with the golden value stored on-chip. It needs no tester, which is why it's the standard way to test logic in the car.

The STUMPS LBIST architecture. Pseudo-random patterns reach roughly 85–95% stuck-at coverage. Test points (extra control/observe points on random-resistant logic) raise it. Any X that reaches the MISR ruins the signature, so all X sources must be bounded.

Aspect	Typical choice
When it runs	Key-on (before radar output is trusted); some SoCs also periodically, per core, while the other lockstep partner covers
Time budget	≈ 10–50 ms at start-up, within the system's boot budget
What it covers	Latent faults in safety mechanisms: lockstep comparators, ECC logic, watchdogs, monitors (ISO 26262 LFM)
Runtime (single-point) faults	Covered instead by lockstep, ECC, CRC, watchdog, plus analog/RF monitors
Hybrid	The same decompressor/LFSR hardware serves both ATE compression and LBIST, which saves area

JTAG and test access standards

Digital

Standard	What it provides	Use in a radar SoC
IEEE 1149.1 (JTAG / boundary scan)	4–5 pin TAP (TCK, TMS, TDI, TDO, TRST), instruction register, boundary-scan cells at the pins, BSDL description	Module board interconnect test, test-mode entry, debug access
IEEE 1149.6	Boundary scan for AC-coupled / differential links	High-speed data outputs (LVDS/CSI-2) where present
IEEE 1500	Core test wrappers	Isolate and test IP cores (DSP, HWA) independently
IEEE 1687 (IJTAG)	Network of on-chip instruments behind JTAG (segment insertion bits, ICL/PDL)	One access path to MBIST controllers, sensors, trim registers, and the analog BIST/BISM instruments

Security. Scan and JTAG can read or write any internal state, including keys and safety configuration. Lock test and debug access in production parts (password/challenge unlock, fused lock, scan reset on mode change), as required by ISO/SAE 21434.

Stress conditions and screening

Screening

Some defects are latent. The part passes a normal test today but fails after weeks in the car: thin gate-oxide spots, marginal vias, weak SRAM cells. Screening applies stress (voltage, temperature, time) to make those defects fail at test, and statistics to reject parts that pass but look abnormal.

Screen	Typical condition	Targets	Where
Voltage stress (HVST)	Core at ≈ 1.3–1.5 × V_nom (below the oxide breakdown limit), ≈ 0.1–1 s, with scan/LBIST toggling or static states	Weak gate oxide, latent shorts: accelerates infant mortality in seconds	Wafer probe (sometimes final)
Burn-in (dynamic)	125–150 °C, elevated V, hours, with scan/LBIST toggling	Infant-mortality failures	Package; often reduced or replaced by HVST + PAT for cost
VLV (very-low-voltage)	Scan/MBIST at ≈ 0.6–0.8 × V_nom (above the functional Vmin)	Resistive opens/bridges, weak transistors: defects hidden by strong drive at nominal V	Wafer / final
Vmin / shmoo	Sweep V (and f) to the pass/fail edge	Marginal parts; a Vmin outlier signals a defect	Characterisation; Vmin used for dynamic PAT
Temperature insertions	Hot (125–150 °C), cold (−40 °C), sometimes room	Temperature-activated defects, leakage, analog drift, timing at hot	Wafer hot; final cold + hot (Grade 1/0)
IDDQ / ΔIDDQ	Static current at several scan states; compare the delta between states and neighbours	Bridges, oxide shorts (leakage at advanced nodes makes absolute IDDQ weak, so use deltas)	Wafer
At-speed with guard band	f_func + margin at low V and hot	Small delay defects	Final
SRAM retention / disturb	Low V, hot, pause time, neighbour hammering	Weak cells	Wafer
RF stress (radar-specific)	PA at max power, hot, for a set time; re-measure Pout	PA degradation, early drift	Final / qualification

Statistical screens (outlier rejection)

PAT / DPAT (AEC-Q001)

Part Average Testing: set limits from the population's robust mean ± 6σ, not just the spec. Dynamic PAT recalculates them per lot or wafer. Parts inside spec but outside the population are likely defective and get rejected.

Robust μ = median, σ = IQR / 1.35 PAT limits = μ ± 6σ (inside spec limits)

Geographic screens

GDBN (good die in bad neighbourhood) and NNR (nearest-neighbour residual) use the wafer map. A passing die surrounded by failing dies, or whose parameters differ from its neighbours', sits in a defect cluster and is rejected. Z-PAT looks at the same die position across wafers. What the patterns mean in the fab: wafer map signatures.

Part-level correlation

Multivariate screens combine parameters such as IDDQ vs Vmin vs ring-oscillator speed. A part whose combination doesn't fit its process corner is an outlier even when each value is normal. The trim values from BIST/BISM (see the BIST page) are useful inputs.

Reliability qualification (AEC-Q100)

Qualification

Qualification is done once per product (and after major changes) on sample lots. It proves the design and process meet the automotive lifetime. Screening then keeps every shipped part in line with the qualified population. The grade sets the ambient range: Grade 1 is −40…+125 °C, Grade 0 is −40…+150 °C, and radar is typically Grade 1 or 2.

Test	What it stresses	Typical condition (grade-dependent)
HTOL: High Temperature Operating Life	Intrinsic wear-out under bias	≈ 1000 h at max rated temperature and V_max, dynamic operation
ELFR: Early Life Failure Rate	Infant mortality in a large sample	Short (e.g. 48 h) high-temperature operation, large sample size
TC: Temperature Cycling	Package, bumps/balls, die attach (failure modes)	e.g. −55 ↔ +150 °C, ≈ 1000 cycles (Grade 0/1)
THB / HAST	Humidity + bias corrosion	85 °C/85% RH 1000 h, or HAST 130 °C/85% RH 96 h
HTSL: High-Temperature Storage Life	Unbiased material and interface stability	≈ 150 °C, 1000 h
ESD (HBM, CDM) and latch-up	Electrostatic and latch-up robustness	HBM ≥ 2 kV, CDM ≥ 500 V (750 V corners); LU per JESD78
Wafer-level reliability	EM, TDDB, HCI, NBTI of the process	Process qualification by the foundry

Conditions above are typical. The exact stress levels, durations and sample sizes are defined in the current AEC-Q100 revision for each grade.

Production test flow (digital + stress)

Wafer probe (CP), insertion 1 at 25 °C: Cres + open/short + power-short → leakage → scan chain test + stuck-at → IDDQ → HVST → IDDQ again → MBIST + repair analysis → VLV scan/MBIST → reference trims and analog/RF BIST/BISM (see the BIST page) → eFuse burn (repair + trims) → verify. Insertion 2 at 125 °C: at-speed transition scan with guard band, hot leakage. The complete flow is on the production test flow page.
Post-probe data: DPAT limits, GDBN/NNR on the wafer map, ink out the outliers.
Assembly (FC-BGA / eWLB).
Final test (FT), cold and hot: reduced scan (at-speed with guard band), MBIST, LBIST self-check, BIST/BISM re-check at temperature, PAT on the key parameters.
Burn-in (if required for the product or customer) → post-burn-in test.
Optional system-level test (SLT): boot the radar firmware and run a chirp frame with loopback; catches interaction defects that structural test misses.
Data feed-forward: per-part data (ECID) links wafer, final and field returns for failure analysis.

Scan test-time calculator

Estimate scan shift time and tester memory for one test insertion. The defaults are a single-chip radar SoC with about 3 M scan flops.

Result

Scan time per device

–

Internal chains

Chain length

Total shift cycles

Pattern data volume

Effective time per device (multi-site)

Same test without compression

DFT checklist for a radar SoC

Architecture

Coverage targets agreed with the customer per fault model (stuck-at, transition, cell-aware, memory)
Compression ratio sized to tester channels and memory
OCC on every at-speed clock domain; PLL usable in test mode
MBIST on all memories, with repair and eFuse; ECC testable
LBIST for key-on latent-fault coverage, with a time budget and test points
IJTAG network reaching MBIST, LBIST, sensors, trims and analog BIST
Test/debug access locked in production

Mixed-signal and stress

Safe state for PA, LO, VCO and LDOs whenever scan is active
Shift power budget checked against on-chip LDO capability; option to supply the rail from the ATE
X sources (ADC, memories, analog) masked or bounded
HVST mode: core rail can be forced high safely; IO and analog protected
VLV and retention modes supported (regulator bypass)
ECID and per-part datalog for PAT, GDBN and field-return traceability

Glossary of abbreviations

Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.

Radar system & ADAS

Abbr.	Stands for	Note
FCW	Forward Collision Warning	Warns of an imminent frontal collision; stage before AEB.
FCTA	Front Cross-Traffic Alert	Front corner-radar function at junctions and driveways.
RCTB	Rear Cross-Traffic Braking	Brakes automatically when RCTA detects cross traffic while reversing.
DOW	Door-Opening Warning	Warns before a door is opened into an approaching cyclist or car.
VRU	Vulnerable Road User	Pedestrians, cyclists and motorcyclists.
TTC	Time To Collision	Range divided by closing speed; triggers warnings and braking.
LRR	Long-Range Radar	Front radar, ≈ 200–300 m, narrow field of view.
MRR	Mid-Range Radar	≈ 80–160 m, ±40–60° field of view.
SRR	Short-Range Radar	Corner radar, ≈ 30–80 m, ±75–90° field of view.
NCAP	New Car Assessment Programme	Consumer safety ratings (Euro NCAP, C-NCAP, IIHS …).
GSR	General Safety Regulation (EU) 2019/2144	Makes AEB and other assistance functions mandatory in the EU.
CPD	Child Presence Detection	In-cabin sensing (often 60 GHz radar) that detects a child left in the car.
ACC	Adaptive Cruise Control	Keeps distance to the car ahead; uses long-range front radar.
ADAS	Advanced Driver-Assistance Systems	The vehicle functions the radar serves.
AEB	Autonomous Emergency Braking	Brakes automatically when a collision is imminent.
BSD	Blind-Spot Detection	Corner-radar function.
LCA	Lane-Change Assist	Corner-radar function that warns of fast approaching vehicles.
RCTA	Rear Cross-Traffic Alert	Rear corner-radar function when reversing.
L2	SAE automation Level 2 (L3 = Level 3)	Partial (L2) and conditional (L3) driving automation.
FMCW	Frequency-Modulated Continuous Wave	A linear chirp; range comes from the beat frequency f_b = S·2R/c.
FoV	Field of View	Angular coverage in azimuth and elevation.
RCS	Radar Cross Section	Target reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0).
dBsm	Decibels relative to 1 m²	Unit of RCS.
EIRP	Effective Isotropic Radiated Power	Tx power + antenna gain; limited by regulations.
MIMO	Multiple-Input Multiple-Output	N_tx × N_rx channels form a larger virtual array.
TDM	Time-Division Multiplexing	One Tx per chirp; v_max falls by a factor of N_tx.
BPM	Binary Phase Modulation	0/180° codes across chirps separate the Tx signals.
DDMA	Doppler-Division Multiple Access	Each Tx gets a slow-time phase ramp and separates in Doppler.
DoA	Direction of Arrival	Angle estimation over the virtual array.
DBF	Digital Beamforming	FFT or matched steering over array channels.
CFAR	Constant False Alarm Rate	Adaptive detection threshold (CA = cell-averaging, OS = ordered-statistic).
FFT	Fast Fourier Transform	Range, Doppler and angle FFTs build the radar cube.
SNR	Signal-to-Noise Ratio
MUSIC	MUltiple SIgnal Classification	Subspace super-resolution DoA algorithm.
ESPRIT	Estimation of Signal Parameters via Rotational Invariance Techniques	Super-resolution DoA algorithm.
IAA	Iterative Adaptive Approach	Super-resolution spectral / DoA estimator.
DBSCAN	Density-Based Spatial Clustering of Applications with Noise	Groups detections into objects.
EKF	Extended Kalman Filter	Nonlinear tracking filter.
UKF	Unscented Kalman Filter	Nonlinear tracking filter using sigma points.
IMM	Interacting Multiple Model	Tracker that mixes several motion models.
HWA	Hardware Accelerator	On-chip FFT / radar processing engine.
RTS	Radar Target Simulator	Echo generator for HIL and EOL testing.
HIL	Hardware-in-the-Loop	Testing the real sensor against simulated scenarios.
EOL	End-of-Line	Final production test of a module or vehicle.

RF & analog front end

Abbr.	Stands for	Note
HPBW	Half-Power Beamwidth	Angle between the −3 dB points of an antenna or array beam.
PDN	Power Delivery Network	Regulators, planes, decoupling and package paths that supply the chip.
PI	Power Integrity	Keeping supply voltage within limits under load steps and noise.
EMI	Electromagnetic Interference	Unwanted emission or pick-up of electromagnetic energy.
BCI	Bulk Current Injection	Immunity test (ISO 11452-4) that injects RF current into a cable harness.
TIM	Thermal Interface Material	Gap pad or paste between board or package and the heat sink.
RF	Radio Frequency	Here the 76–81 GHz signal.
LO	Local Oscillator	The chirp signal that drives the Tx and the Rx mixers.
IF	Intermediate Frequency	The beat / baseband signal after the mixer, DC–20 MHz.
PA	Power Amplifier	Tx output stage, 12–14 dBm.
LNA	Low-Noise Amplifier	First Rx stage; sets most of the NF.
NF	Noise Figure	Noise the receiver adds, in dB.
VGA	Variable-Gain Amplifier	Programmable-gain stage (IF), or signed VGAs in the phase rotator.
TIA	Transimpedance Amplifier	Current-to-voltage stage after a passive mixer.
HPF	High-Pass Filter	In IF: removes leakage and DC, and equalises R⁻⁴.
LPF	Low-Pass Filter
AAF	Anti-Aliasing Filter	Low-pass filter in front of the ADC.
PPF	Polyphase Filter	RC-CR network that generates I/Q.
I/Q	In-phase / Quadrature	Two copies of a signal 90° apart.
IRR	Image Rejection Ratio	How well an I/Q path suppresses the mirror frequency.
SSB	Single Sideband	A frequency shift in one direction only, e.g. the loopback offset.
BPSK	Binary Phase-Shift Keying	0/180° switching; produces ±f_m sidebands.
VM	Vector Modulator	I/Q-weighted phase rotator.
RTPS	Reflection-Type Phase Shifter	Hybrid coupler terminated by tunable loads.
P1dB	1 dB compression point	Input (or output) level where gain drops by 1 dB.
IIP3	Input third-order intercept point	Linearity figure; cascades with the gain before each stage.
PAE	Power-Added Efficiency	(P_out − P_in) / P_DC of a PA.
Psat	Saturated output power	Maximum output power of a PA.
DSB	Double Sideband	Noise figure counting both sidebands (typical for zero-IF mixers).
PGA	Programmable-Gain Amplifier	IF VGA with digitally set gain steps.
AGC	Automatic Gain Control	Loop that sets the VGA gain from the signal level.
HD2	2nd-order Harmonic Distortion (HD3 = 3rd)	Harmonics show up as ghost targets at 2×/3× range.
AM/PM	Amplitude-to-phase conversion	Phase change caused by amplitude or supply changes.
RL	Return Loss	Match quality, in dB.
Cpl	Coupler (directional coupler)	Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback.
PD	Power Detector	Diode or square-law RF-to-DC converter.
APC	Automatic Power Control	Closed loop from the power detector to the VGA/PA gain code.
DPD	Digital Predistortion	Wideband PA linearisation used in comms; radar uses static gain/phase LUTs instead.
VSWR	Voltage Standing-Wave Ratio	Mismatch at the antenna/load; changes the delivered power.
CW	Continuous Wave	An unmodulated single-frequency tone.
ENR	Excess Noise Ratio	Calibrated output level of a noise source.
SiGe	Silicon-Germanium (BiCMOS)	Bipolar-plus-CMOS process used for earlier radar chips.
CMOS	Complementary Metal-Oxide-Semiconductor	RFCMOS = CMOS process with RF / mmWave capability.
RFCMOS	RF-capable CMOS	Today's single-chip radar process (e.g. 45/40/28/22 nm).
NMOS	N-channel MOS transistor (PMOS = P-channel)
PTAT	Proportional To Absolute Temperature	Voltage or current used by temperature sensors.
BG	Bandgap reference	Temperature-stable voltage reference (BG1/BG2 = two independent ones).
PVT	Process, Voltage, Temperature	Variation corners a design must cover.

LO, clock & synthesis

Abbr.	Stands for	Note
PLL	Phase-Locked Loop	Locks the VCO to the crystal and generates the ramp.
ADPLL	All-Digital PLL	PLL with a TDC and a digital loop filter.
VCO	Voltage-Controlled Oscillator	≈ 19–20.25 GHz, multiplied ×4 to 77 GHz.
PFD	Phase-Frequency Detector	Compares the divided VCO with the reference.
CP	Charge Pump; also Chip Probe	In a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test.
TDC	Time-to-Digital Converter	Digital phase detector of an ADPLL.
XTAL	Crystal (reference oscillator)	40/50 MHz reference for PLL, ADC and digital.
DDS	Direct Digital Synthesizer	Digitally generated tone (IF test tone).
Kvco	VCO gain	Tuning sensitivity in MHz/V; varies per band.
AFC	Automatic Frequency Calibration (band calibration)	Picks the VCO capacitor-bank band before the PLL closes.
MMD	Multi-Modulus Divider	Programmable divider in the PLL feedback, dithered by the ΣΔ modulator.
CML	Current-Mode Logic	Fast differential logic used for the first divider (prescaler) stages at 20 GHz.

Data conversion & digital

Abbr.	Stands for	Note
SNM	Static Noise Margin	Noise an SRAM cell tolerates before flipping; read SNM is the critical one.
SEU	Single-Event Upset	Bit flip caused by a particle strike (soft error).
SER	Soft-Error Rate	Rate of radiation-induced bit flips, in FIT per Mbit.
MBU	Multi-Bit Upset	One particle flips several neighbouring cells.
RDF	Random Dopant Fluctuation	Random number of dopant atoms in a small channel; main cause of Vth mismatch.
LER	Line-Edge Roughness	Rough gate edges that add Vth variation in small devices.
NPSF	Neighbourhood Pattern-Sensitive Fault	Memory cell fails only for certain data in its neighbours.
SEC-DED	Single-Error Correction, Double-Error Detection	ECC code used on memory words (e.g. 64 + 8 bits).
ROM	Read-Only Memory	Mask-programmed memory for boot code and tables.
DRF	Data-Retention Fault	Memory cell loses its value after a pause.
WL	Word Line	Row select line of a memory array.
BL	Bit Line	Column data line of a memory array (BL and its complement BLB).
OSR	Oversampling Ratio	fs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR.
NTF	Noise Transfer Function	How a ΣΔ loop shapes quantisation noise out of the signal band.
SNDR	Signal-to-Noise-and-Distortion Ratio	ENOB = (SNDR − 1.76) / 6.02.
GBW	Gain-Bandwidth product	Op-amp figure of merit; sets filter and PGA accuracy at IF.
CMRR	Common-Mode Rejection Ratio	How well a differential circuit rejects signals common to both inputs.
CSI-2	MIPI Camera Serial Interface 2	High-speed serial link used for raw radar data.
TSN	Time-Sensitive Networking	Deterministic automotive Ethernet (IEEE 802.1).
ADC	Analog-to-Digital Converter	Main Rx ADCs (ΣΔ) and the aux SAR ADC.
DAC	Digital-to-Analog Converter	Rotator I/Q weights, bias, trim, test-tone generation.
SAR	Successive-Approximation Register ADC	Slow, precise ADC used for monitoring.
CT	Continuous-Time (CT-ΣΔ)	Sigma-delta ADC with a continuous-time loop filter.
ENOB	Effective Number of Bits
SFDR	Spurious-Free Dynamic Range	Tone relative to the largest spur.
THD	Total Harmonic Distortion
DR	Dynamic Range
INL	Integral Nonlinearity	Deviation from the ideal transfer line.
DNL	Differential Nonlinearity	Deviation of each step from 1 LSB.
LSB	Least Significant Bit (MSB = most significant)
DFE	Digital Front End	Decimation, DC and I/Q correction, interference handling.
CIC	Cascaded Integrator-Comb	Multiplier-free decimation filter.
FIR	Finite Impulse Response filter
DSP	Digital Signal Processor
MCU	Microcontroller Unit
CPU	Central Processing Unit	E.g. the RF control CPU that runs chirps and monitors.
SoC	System-on-Chip
ECU	Electronic Control Unit	Vehicle computer that receives radar data.
SRAM	Static RAM (RAM = random-access memory)
ECC	Error-Correcting Code	Memory protection for functional safety.
DMA	Direct Memory Access
LUT	Look-Up Table	E.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature.
FW	Firmware (SW = software)
OTP	One-Time Programmable memory	Holds trims and IDs, like eFuse.
SPI	Serial Peripheral Interface	Configuration / test bus from host or ATE.
CAN	Controller Area Network (CAN-FD = Flexible Data-rate)	Vehicle bus for object lists.
ETH	Ethernet (100/1000BASE-T1)	Automotive single-pair Ethernet.
CSI	Camera Serial Interface (MIPI CSI-2)	Streams raw radar data to a central SoC.
LVDS	Low-Voltage Differential Signaling	Raw-data debug / streaming interface.
GPIO	General-Purpose Input/Output
IO	Input/Output

Power

Abbr.	Stands for	Note
LDO	Low-Dropout regulator	Linear regulator; one per noise-sensitive domain.
PMIC	Power-Management IC	External bucks, supervisors and watchdog.
PSRR	Power-Supply Rejection Ratio	How much supply ripple an LDO (or circuit) blocks.
UV	Under-Voltage (OV = Over-Voltage)	Supply monitors, a safety mechanism.
OV	Over-Voltage	Rail above its window; OV monitor protects gate oxides.
POR	Power-On Reset	Holds the chip in reset until all rails are valid.
BOR	Brown-Out Reset	Resets when a supply sags during operation.
ESR	Equivalent Series Resistance	Of the LDO output capacitor; its zero affects loop stability.
OCP	Over-Current Protection	Current limit on a regulator output.
Iq	Quiescent current	Current a regulator draws for itself with no load.
DLDO	Digital LDO	Switched pass-device array regulated by a comparator loop.
GND	Ground

Test & production

Abbr.	Stands for	Note
EVB	Evaluation Board	Board that carries the chip on the bench with supplies, clock, interfaces and RF transitions.
SMU	Source-Measure Unit	Precision instrument that forces voltage or current and measures the other.
OTA	Over The Air	Measurement through antennas in a chamber instead of a cable or waveguide.
GSG	Ground-Signal-Ground probe	RF wafer probe with a signal tip between two ground tips.
LRRM	Line-Reflect-Reflect-Match calibration	On-wafer VNA calibration method for mmWave probes.
SCPI	Standard Commands for Programmable Instruments	Text command set used to automate instruments.
UPH	Units Per Hour	Test throughput of a tester and handler.
eFuse	Electrically programmable fuse	Silicided poly link blown by current; stores trim, ID and repair bits.
MTP	Multiple-Time Programmable memory	Small NVM that can be rewritten a few times.
NVM	Non-Volatile Memory	Keeps data without power: eFuse, OTP, MTP, flash.
VPP	Programming supply voltage	Supply used only to program fuses or OTP.
CRC	Cyclic Redundancy Check	Checksum that detects corrupted data, e.g. trim words at boot.
RMA	Return Material Authorization	A customer return, analysed through the 8D process.
8D	Eight Disciplines	Structured problem solving: team, describe, contain, root cause, correct, verify, prevent, close.
MSA	Measurement System Analysis	Proves a measurement is precise and accurate enough (Gage R&R, bias, stability).
GRR	Gage Repeatability and Reproducibility	%GRR < 10 % of tolerance is good.
BIST	Built-In Self-Test	On-chip stimulus + measurement; result is pass/fail or a value checked against a limit.
BISM	Built-In Self-Measurement	Same on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend.
DFT	Design for Test
ATE	Automatic Test Equipment	Production tester.
ATPG	Automatic Test Pattern Generation	Scan patterns for digital logic.
IDDQ	Quiescent supply-current test	Detects leakage defects.
PMU	Parametric Measurement Unit	ATE DC source/measure channel.
Cres	Contact resistance	Probe or socket contact resistance; measured with the Kelvin or two-current method.
FIMV	Force Current, Measure Voltage	PMU mode used for open/short (diode) tests.
FVMI	Force Voltage, Measure Current	PMU mode used for leakage and power-short tests.
IIL	Input leakage current, input Low (IIH = input High)	Leakage limit per IO pin, typically \|I\| < 1 µA.
IIH	Input leakage current, input High
ESD	Electrostatic Discharge	Pad protection diodes / clamps; the diode method uses them for continuity.
VDD	Positive supply rail (VSS = ground / negative rail)
VSS	Ground / negative supply rail
DCR	DC Resistance	E.g. of an RF shunt inductor, 0.5–3 Ω.
Hi-Z	High impedance (Z)	Output driver switched off; the pin floats.
OE	Output Enable	Control that switches an output between driving and Hi-Z.
IOZ	Off-state output leakage (IOZH at VDDIO, IOZL at 0 V)	Measured on a pin in Hi-Z; typically \|I\| < 1–10 µA.
VOH	Output High voltage threshold (VOL = Output Low)	Tester comparator levels that decide 1 / Z / 0.
VOL	Output Low voltage threshold
HIGHZ	IEEE 1149.1 instruction that puts all outputs in Hi-Z
EXTEST	IEEE 1149.1 external test instruction	Boundary cells drive and sample the pins; used for interconnect and walking-Z tests.
RPCT	Reduced Pin-Count Testing	Testing through JTAG / a few pins, so more sites fit on one tester.
BICS	Built-In Current Sensor	On-chip current monitor for IDDQ per power domain.
SPC	Statistical Process Control
VNA	Vector Network Analyzer	Lab instrument for S-parameters.
AWG	Arbitrary Waveform Generator
DMM	Digital Multimeter
GPIB	General-Purpose Interface Bus	Instrument control bus (like LAN).

Safety, standards & regulation

Abbr.	Stands for	Note
PMHF	Probabilistic Metric for random Hardware Failures	ISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D.
SEooC	Safety Element out of Context	A part developed to ISO 26262 against assumed system requirements.
FMEA	Failure Mode and Effects Analysis	Qualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage.
FIT	Failures In Time	Failures per 10⁹ device-hours.
MTTF	Mean Time To Failure
RED	Radio Equipment Directive (EU 2014/53/EU)	EU conformity framework for radio transmitters, including radar.
ASIL	Automotive Safety Integrity Level	ISO 26262 risk class A–D; radar typically ASIL-B.
ISO	ISO 26262 / ISO/SAE 21434 / ISO 11452	Functional safety / cybersecurity / EMC immunity.
FTTI	Fault-Tolerant Time Interval	Time from fault to hazard; monitors must react within it.
FMEDA	Failure Modes, Effects and Diagnostic Analysis
SPFM	Single-Point Fault Metric	ISO 26262 coverage metric.
LFM	Latent Fault Metric	ISO 26262 coverage metric.
AEC	Automotive Electronics Council (AEC-Q100 / Q200)	Qualification of ICs / passives.
ETSI	European Telecommunications Standards Institute	EN 301 091 / EN 303 396 radar standards.
FCC	Federal Communications Commission	US rules, Part 95M for 76–81 GHz.
EMC	Electromagnetic Compatibility
CISPR	Comité International Spécial des Perturbations Radioélectriques	CISPR 25: vehicle-component emissions.
OOB	Out-of-Band (emission)

Digital DFT, stress & reliability

Abbr.	Stands for	Note
UHST	Unbiased Highly Accelerated Stress Test	HAST without bias, 130 °C / 85 % RH; alternative to autoclave.
PTC	Power Temperature Cycling	Temperature cycling with the device powered on and off.
EDR	Endurance and Data Retention	Qualification of non-volatile memory (AEC-Q100-005).
DPA	Destructive Physical Analysis	Opening and sectioning parts to inspect their construction and damage.
SEM	Scanning Electron Microscope	High-magnification imaging of cross-sections and surfaces.
EDX	Energy-Dispersive X-ray spectroscopy	Element analysis in the SEM: corrosion, contamination, IMC phases.
FIB	Focused Ion Beam	Precise local cutting and imaging; also used for circuit edits.
LTPD	Lot Tolerance Percent Defective	Defect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %.
PC	Preconditioning	Bake, moisture soak and reflow before environmental stress (JESD22-A113).
BLR	Board-Level Reliability	Reliability of the package soldered on a PCB (temperature cycling, drop, vibration).
SAC	Tin-Silver-Copper solder	Lead-free solder alloy (e.g. SAC305) used for balls.
PPAP	Production Part Approval Process	Automotive approval package, includes the qualification report.
DRC	Design Rule Check	Verifies layout against foundry manufacturing rules.
LVS	Layout Versus Schematic	Verifies that the layout matches the schematic netlist.
PEX	Parasitic Extraction	Extracts resistance, capacitance (and inductance) of the layout for post-layout simulation.
AMS	Analog / Mixed-Signal simulation	Simulation that combines transistor-level analog with digital models.
ECO	Engineering Change Order	Late design fix; a metal-only ECO changes only upper masks.
SCR	Silicon-Controlled Rectifier	Thyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up.
GGNMOS	Grounded-Gate NMOS	ESD clamp that works by parasitic-bipolar snapback.
SE	Scan Enable	Selects shift (SE = 1) or functional capture (SE = 0) in scan flops.
SAF	Stuck-At Fault	Node permanently 0 or 1.
TDF	Transition Delay Fault	Node slow to rise or fall; needs at-speed test.
STA	Static Timing Analysis	Finds the longest paths for timing-aware ATPG.
OCV	On-Chip Variation	Timing derates in STA that account for local (mismatch) variation across the die.
OCC	On-Chip Clock Controller	Gates exact launch/capture pulses from the PLL for at-speed test.
LOC	Launch-On-Capture	At-speed scheme; also called broadside.
LOS	Launch-On-Shift	At-speed scheme; SE must switch at speed.
EDT	Embedded Deterministic Test	Scan compression (decompressor + compactor).
LFSR	Linear-Feedback Shift Register	Pseudo-random sequence generator.
PRPG	Pseudo-Random Pattern Generator	LFSR that feeds the scan chains in LBIST.
MISR	Multiple-Input Signature Register	Compresses responses into one signature.
STUMPS	Self-Test Using MISR and Parallel Shift-register sequence generator	Standard LBIST architecture.
LBIST	Logic BIST	On-chip random-pattern scan test; used at key-on.
MBIST	Memory BIST	On-chip March-algorithm test of SRAMs.
BIRA	Built-In Redundancy Analysis	Computes which spare rows/columns repair a memory.
BISR	Built-In Self-Repair	Loads the repair from eFuse at boot.
IR	IR drop	Supply voltage drop (current × resistance), high during scan shift.
JTAG	Joint Test Action Group (IEEE 1149.1)	Boundary scan and test access port.
TAP	Test Access Port	JTAG pins TCK, TMS, TDI, TDO, TRST.
BSDL	Boundary Scan Description Language	Describes a chip's JTAG boundary-scan cells.
IJTAG	Internal JTAG (IEEE 1687)	Network for accessing on-chip instruments.
MUX	Multiplexer	Selects one of N inputs; in test, routes sub-block nodes to shared instruments.
ATB	Analog Test Bus	Chip-wide wire pair (force + sense) that test muxes connect sub-block nodes to.
TG	Transmission Gate	Parallel NMOS + PMOS switch; passes the full voltage range.
SPDT	Single-Pole Double-Throw switch	One input to one of two outputs (SP4T = one of four).
BBM	Break-Before-Make	Switching order that opens the old path before closing the new one.
ICL	Instrument Connectivity Language (PDL = Procedural Description Language)	IJTAG description files.
ECID	Electronic Chip ID	Unique per-die ID for traceability.
HVST	High-Voltage Stress Test	Short over-voltage on the core rail to activate latent oxide defects.
VLV	Very-Low-Voltage test	Test below nominal V to expose resistive defects.
Vmin	Minimum operating voltage	The pass/fail edge in a shmoo; an outlier Vmin flags a defect.
PAT	Part Average Testing (AEC-Q001)	Outlier limits at robust μ ± 6σ.
DPAT	Dynamic Part Average Testing	PAT limits recalculated per lot or wafer.
GDBN	Good Die in Bad Neighbourhood	Wafer-map screen that rejects dies in defect clusters.
NNR	Nearest-Neighbour Residual	Compares a die's parameter with its wafer neighbours.
DPPM	Defective Parts Per Million	Shipped-quality metric; automotive target ≪ 1.
FT	Final Test	Package-level production test.
SLT	System-Level Test	Functional test by booting the application.
PCM	Process Control Monitor	Test structures in the scribe lines, measured by the fab (see WAT).
WAT	Wafer Acceptance Test	Fab's electrical test of PCM structures before shipping wafers.
OSAT	Outsourced Semiconductor Assembly and Test	Company that packages and tests the dies.
QA	Quality Assurance	Sample-based outgoing inspection and audits.
Cp	Process capability (Cp)	(USL − LSL) / 6σ: spec width vs process spread.
Cpk	Process capability index	min(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67.
USL	Upper Spec Limit (LSL = Lower Spec Limit)	Design limits; outside them the part is out of spec.
LSL	Lower Spec Limit
UCL	Upper Control Limit (LCL = Lower Control Limit)	Process limits from history, usually mean ± 3σ.
LCL	Lower Control Limit
OCAP	Out-of-Control Action Plan	Documented steps when an SPC rule fires.
MRB	Material Review Board	Decides what happens to held material: release, rework, scrap or deviation.
MIM	Metal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal)	Precision on-chip capacitors.
MOM	Metal-Oxide-Metal (finger) capacitor
BSIM	Berkeley Short-channel IGFET Model	Industry-standard compact transistor model family used in design kits.
Vt	Threshold voltage	Gate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD.
Idsat	Saturation drain current	Id at Vgs = Vds = VDD, per µm of width; transistor strength.
Ioff	Off-state leakage current	Id at Vgs = 0, Vds = VDD.
DIBL	Drain-Induced Barrier Lowering	Vt drop per volt of Vds in short-channel devices.
SS	Subthreshold swing (also SS = slow-slow process corner)	mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature.
TT	Typical-typical process corner	FF = fast-fast; FS / SF = skewed NMOS / PMOS corners.
FF	Fast-fast process corner
gm	Transconductance	∂Id/∂Vgs; the transistor's gain.
gds	Output conductance	∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds).
Cox	Gate-oxide capacitance per area	εox / Tox.
Tox	Gate-oxide thickness	Measured with C-V structures in WAT.
fT	Transit (unity current-gain) frequency	≈ gm / 2π(Cgs + Cgd).
fmax	Maximum oscillation (unity power-gain) frequency	Needs ≈ 3–4× the operating frequency for useful gain.
Vbd	Gate-oxide breakdown voltage	Voltage where oxide current jumps past compliance in a V-ramp test.
BV	Breakdown Voltage	BVdss = drain-source (gate off), BVj = junction.
BVdss	Drain-source breakdown voltage	Transistor off-state breakdown; limits PA drain swing.
BVj	Junction breakdown voltage	Reverse breakdown of N+/P-well or P+/N-well diodes.
TLP	Transmission-Line Pulse	ESD device characterisation with short, high-current pulses.
QBD	Charge to breakdown	Total charge an oxide passes before breaking down (reliability).
IMD	Inter-Metal Dielectric	Insulator between metal lines/layers; tested with comb structures.
CMP	Chemical-Mechanical Planarization	Polishing step that flattens each layer; source of centre, edge and ring signatures.
OPC	Optical Proximity Correction	Mask shape corrections; weak spots (hotspots) can fail per reticle shot.
EBR	Edge Bead Removal	Removes resist build-up at the wafer edge.
D0	Defect density	Random defects per unit area; baseline yield Y ≈ e^(−D0·A).
HTOL	High-Temperature Operating Life	≈ 1000 h biased at max temperature (AEC-Q100).
ELFR	Early Life Failure Rate	Short high-temperature operation of a large sample.
TC	Temperature Cycling	Package and interconnect fatigue test.
THB	Temperature-Humidity-Bias	85 °C / 85% RH with bias.
HAST	Highly Accelerated Stress Test	130 °C / 85% RH with bias.
RH	Relative Humidity
HTSL	High-Temperature Storage Life	Unbiased bake.
HBM	Human-Body Model (ESD)
CDM	Charged-Device Model (ESD)
LU	Latch-Up	JESD78 test.
EM	Electromigration	Metal wear-out under current (wafer-level reliability).
TDDB	Time-Dependent Dielectric Breakdown	Gate-oxide wear-out.
HCI	Hot-Carrier Injection	Transistor degradation mechanism.
NBTI	Negative-Bias Temperature Instability	PMOS threshold drift.

PCB, package & materials

Abbr.	Stands for	Note
TCB	Thermo-Compression Bonding	Flip-chip attach with heat and force per die; fine pitch, low warpage.
MUF	Molded Underfill	Mold compound that also fills the gap under a flip-chip die.
CSAM	C-mode Scanning Acoustic Microscopy	Ultrasound imaging of voids and delamination inside packages.
AOI	Automated Optical Inspection	Camera inspection of RDL, bumps and balls in the assembly line.
KGD	Known-Good Die	Die that passed wafer sort and is released for assembly.
WLP	Wafer-Level Package	Package built on the whole wafer (fan-in) or a reconstituted wafer (fan-out).
PCB	Printed Circuit Board
RDL	Redistribution Layer	Thin-film Cu wiring that routes die pads to balls (fan-out) or bumps.
UBM	Under-Bump Metallisation	Metal stack between die/RDL pad and the solder.
FOWLP	Fan-Out Wafer-Level Package	Die embedded in mold with RDL fanning out to balls; eWLB is one type.
CSP	Chip-Scale Package	Package only slightly larger than the die (FC-CSP = flip-chip CSP).
AiP	Antenna-in-Package	Antennas built into package layers.
IMC	Intermetallic Compound	Layer formed between solder and UBM/pad; grows with time and temperature.
CTE	Coefficient of Thermal Expansion	Mismatch between materials drives solder and bump fatigue.
MSL	Moisture Sensitivity Level	J-STD-020 rating: how long a package may sit out of dry pack before reflow.
ELK	Extreme Low-k dielectric	Fragile back-end dielectric in advanced nodes; cracks under bump stress.
NSMD	Non-Solder-Mask-Defined pad	PCB pad style that improves solder-joint fatigue life.
Dk	Dielectric constant	Sets line impedance and antenna tuning; shifts with moisture.
Df	Dissipation factor	Dielectric loss; key for RF loss at 77 GHz.
C-SAM	C-mode Scanning Acoustic Microscopy	Non-destructive imaging of delamination and voids.
PBO	Polybenzoxazole	Polymer dielectric used in RDL (like polyimide).
EOS	Electrical Overstress	Damage from overvoltage or overcurrent beyond ESD events.
BGA	Ball Grid Array	FC-BGA = flip-chip BGA.
eWLB	embedded Wafer-Level Ball-grid-array	Fan-out package with low RF loss.
AoP	Antenna-on-Package
LoP	Launch-on-Package	RF launched from package into waveguide / antenna.
GCPW	Grounded Coplanar Waveguide	PCB transmission line at the ball launch.
SIW	Substrate-Integrated Waveguide	Waveguide formed with via fences in the PCB.
FR4	Flame-Retardant epoxy-glass laminate	Standard low-cost PCB material.
ENEPIG	Electroless Nickel, Electroless Palladium, Immersion Gold	PCB surface finish.
ImAg	Immersion Silver	PCB surface finish.
HASL	Hot-Air Solder Leveling	Surface finish; too rough/uneven for 77 GHz.
PBT	Polybutylene terephthalate (PC = polycarbonate)	Radome plastics.
HFSS	High-Frequency Structure Simulator (Ansys)	3D EM simulator (CST = Dassault's equivalent).