77 GHz radar, from antenna to object list

The transmit and receive paths share one LO. A fractional-N PLL generates a linear frequency ramp at about 20 GHz. A ×4 multiplier brings it up to 77 GHz, and the result drives both the PA and the Rx mixers. Because each Rx mixer multiplies the echo by the chirp being transmitted at that moment, a target shows up as a low beat frequency (a few MHz). That is why a modest ADC can digitise a signal with GHz of bandwidth. Click a block to jump to its section.

Everything downstream comes from a few top-level numbers: maximum range, range resolution, maximum and resolvable velocity, field of view and angular resolution, update rate, and the smallest target that must be detected at that range. Pick the sensor class first.

Relations that tie spec to hardware

Plug your own numbers into these with the calculator.

At 77 GHz, λ₀ = 3.9 mm, so λ/2 is about 1.95 mm. That makes a 12- to 192-element virtual array fit in a palm-sized module. The antenna sets gain, beamwidth, sidelobes and, through the MIMO layout, angular resolution. For long-range designs it is usually the biggest factor in the link budget.

Antenna options

PCB and transition spec (patch array case)

MIMO virtual array

With TDM, DDMA or BPM, each Tx/Rx pair acts as an element at position (x_tx + x_rx). Spacing the Tx elements N_rx·λ/2 apart fills a contiguous virtual array of N_tx·N_rx elements with λ/2 spacing. The aperture grows without adding Rx channels.

Each Tx channel takes the 77 GHz LO, applies a programmable phase (for BPM/DDMA MIMO coding and beam steering), amplifies it, and sends it to the antenna. The coupler and power detector at the output feed the monitoring ADC.

Tx multiplexing options

• TDM: one Tx per chirp. Simple, with perfect separation, but v_max falls by a factor of N_tx and Doppler must be compensated before angle FFT.
• BPM: all Tx on, with Hadamard phase codes across chirps. It gains SNR (a factor of N_tx in power) but needs the target to stay coherent over the code length.
• DDMA: each Tx gets a slow-time phase ramp, so the Tx signals separate in the Doppler spectrum. Keeps full SNR, and is the choice for most imaging radars. Needs empty Doppler bands, or non-uniform offsets to resolve ambiguity.

Each Tx channel needs a fast, fine-grained phase control, used for BPM/DDMA MIMO codes, beam steering, and calibrating out channel mismatch. At 77 GHz the usual solution is an active vector-modulator phase rotator. It splits the LO into quadrature components I (0°) and Q (90°), weights each with a signed variable-gain stage set by a current DAC, and sums them:

Phase shifter or phase rotator?

The two terms are often used for the same Tx block, but they aren't identical. Phase shifter is the general term for any circuit that applies a controlled phase shift. A phase rotator is a phase shifter that can turn the phase continuously through the full 360° and keep going past it with no jump (endless rotation). In practice that almost always means the I/Q vector-interpolation type shown below; SerDes and clock-recovery circuits use the same idea under the name phase interpolator. Datasheets use both names: TI's AWR parts, for example, call the block a "Tx phase shifter", but it is built as a vector-modulator rotator. This page calls it a phase rotator throughout.

Rotator architectures compared

Rotator and DAC specification

The DAC implementation

• Current-steering, sign-magnitude: binary-weighted LSBs plus unary (thermometer) MSBs for monotonicity. The sign bit switches the Gilbert cell's LO polarity, so the DAC itself is unipolar.
• Output: the DAC current is the VGA tail current (or its gain-control bias). Keep the cascode headroom, and match the unit cells, placed in common-centroid layout.
• Linearise in the LUT, not in analog: the VGA's gain vs. current is not linear. Measure the real (a_I, a_Q) → phase/amplitude map with the loopback BIST, and store the inverse as the LUT.
• Timing: double-buffer the DAC registers and update them on the timing engine's chirp-start strobe, so every Tx switches in the same idle window.

DAC linearity specification

There's no radar-specific standard for DAC linearity. The terms and test methods follow IEEE Std 1658 (DAC terminology and test methods), and each block's limits come from its own error budget. For the rotator, the budget is simple geometry. An error of δ LSB on one axis at full-scale code M moves the output vector sideways by δ, which rotates it by up to δ/M radians when the error is perpendicular to the vector:

DNL < 0.5 LSB guarantees monotonicity, so adjacent phase codes never swap order. After BIST calibration the LUT also cancels static INL, so the raw INL limit protects the uncalibrated state and the size of the correction, not the final accuracy.

Linearity specs for each DAC in the radar SoC

What is DAC "bow"?

Bow is shorthand for a bow-shaped INL curve. Plotted against code, the error is zero at both ends and largest near mid-scale, like an arch. INL is measured against the straight line through the end points, so any gentle second-order curvature of the transfer function appears as a bow. It is the most common systematic INL shape in current-steering DACs.

• In the rotator, the load adds its own bow. The DAC current sets the Gilbert-cell VGA gain, and gain vs. tail current is curved. So even a perfect DAC shows bow at the RF output. That is one reason the rotator is calibrated end-to-end through the loopback rather than DAC-only.
• What it does to the rotator: for most phase codes, I and Q sit at different points on the bow, so they get different errors. The output vector is therefore both scaled and rotated. The constellation bulges out (positive bow) or dents in (negative bow) between the axes, giving amplitude ripple and phase error even with perfect I/Q balance.
• Size of the effect (7-bit DAC, perfect I/Q, from the explorer's model): 3 LSB of bow gives about 1.4° RMS phase error and 0.55 dB amplitude ripple, most of a 2° budget. At 1 LSB (the spec) it is about three times smaller. Try it in the explorer below, whose "DAC INL bow" input uses e(m) = INL_peak · 4·(m/M)·(1 − m/M) on both DACs.

Phase-rotator error explorer

This models a 6-bit rotator (64 codes) with your DAC resolution, DAC nonlinearity and quadrature errors. "Raw" uses ideal cos/sin codes. "LUT-corrected" pre-distorts the codes to cancel the I/Q gain/phase imbalance. DAC INL (a bow-shaped error, peak at mid-scale) and random per-code mismatch (a fixed seed, so the plot is repeatable) are applied to both I and Q DACs in either mode. Set both to 0 to see an ideal DAC.

An FMCW chirp is a single tone of constant amplitude, so the wideband digital predistortion (DPD) used for communication PAs isn't needed: there is no modulation for PA nonlinearity to distort. In a radar Tx, "predistortion" means static correction tables, built from power-detector readings, that pre-shape the codes sent to the VGA and phase rotator. The antenna then gets exactly the target power, in equal dB steps, with the intended phase, over temperature. The same detector also provides the ISO 26262 Tx-power monitor and supports the EIRP limit.

The power detector: RF to DC

The coupler (about −20 dB) sets the detector input at roughly −10 to −30 dBm, inside its accurate range, while costing the PA only about 0.05 dB. A second detector on the coupler's reverse port measures reflected power (ball break or antenna open, see BIST path A).

Three predistortion tables

How the loop runs

• Never change gain inside a chirp. That would add amplitude modulation, which shows up as spurs in the range FFT. Codes change in the idle time between chirps or frames, double-buffered like the rotator DACs.
• Loop bandwidth stays far below the frame rate. The loop only tracks temperature and drift, so it can't interact with the radar signal.
• Monitor and limit: if measured power disagrees with the table's expectation beyond a threshold, the monitor raises a safety fault. A hard ceiling on the code keeps EIRP within the regulatory limit even if the loop misbehaves.

Calibration flow

1. Detector trim (wafer or final test): apply two known power levels via the tester or a loopback reference, then store slope and intercept (BIST recipe).
2. Gain sweep at two or three temperatures: VGA code vs P_out from the detector → gain LUT, interpolated in temperature.
3. AM/PM sweep: Tx phase vs gain code, measured through the RF loopback (phase of the FFT tone) → phase correction per code.
4. Runtime: the hybrid loop trims the gain, and the monitor checks the result every frame.

Typical specs

FMCW radar has no separate upconversion mixer. The transmitted signal is the LO. A fractional-N PLL with a ramp generator (sigma-delta modulated divider) sweeps a VCO at about 19–20.25 GHz, and a frequency multiplier (×4, or ×2 from a ~38 GHz VCO) brings it up to 76–81 GHz. The same LO then drives every Rx mixer. This sharing is why close-in phase noise largely cancels at short range (range correlation).

Full detail of the loop, locking, VCO design, voltage swings, failure modes and PCM/WAT links: frequency synthesizer page.

Why the key specs matter

• Ramp nonlinearity spreads a target's beat tone over several range bins, which blurs range and raises sidelobes around strong targets. Its effect grows with range, because the error builds up over the delay τ.
• Phase noise is suppressed by the range-correlation term 2·sin(π·f_off·τ). It cancels for nearby clutter such as the bumper and radome, but at long range the phase-noise skirt of a strong reflector can hide a weak target nearby (a pedestrian next to a truck).
• Spurs from the fractional-N divider show up as ghost targets. Keep them below about −70 dBc, or place them outside the IF band you use.

The echo, delayed by τ = 2R/c, mixes with the chirp being transmitted at that moment. Their difference is a constant beat frequency f_b = S·τ, plus a Doppler term f_d = 2v/λ. This "stretch processing" turns a 1–4 GHz sweep into a DC–20 MHz IF signal.

Circuit-level detail of the LNA, mixer, PA and VGA with parameter tables: RF front-end circuits page.

Real vs complex (I/Q) baseband

A real mixer folds positive and negative IF on top of each other, so noise from the image band adds about 3 dB. It also cannot tell interference or folded spurs apart from real targets. A complex I/Q baseband keeps the full F_s as usable IF bandwidth, rejects that noise, and makes it much easier to detect radar-to-radar interference. The cost is twice the IF and ADC hardware per channel.

A radar MMIC needs quadrature LO signals in three places: the Rx complex mixers (I and Q LO for each Rx), the Tx phase rotator (I and Q inputs to the vector modulator), and the loopback SSB modulator used by BIST. They all have the same problem: making two copies of a 76–81 GHz signal exactly 90° apart and equal in amplitude, over a 5 GHz band and −40…150 °C.

Generate quadrature at the final frequency

The LO is made at about 20 GHz and multiplied ×4, and the multiplier multiplies phase as well. A 90° I/Q split made at 20 GHz becomes 360° after ×4, which is useless. Quadrature therefore has to be created after the multiplier, at 77 GHz. The one exception is a deliberate 22.5° split at 20 GHz, which ×4 turns into 90°, but then every phase error is also multiplied by four.

Rx I/Q mixer design

• Passive (switching) mixers in CMOS: best linearity and lowest flicker noise, which matters because near targets sit at low IF. They need a large, well-defined LO swing, so the LO buffers must be strong.
• Active Gilbert mixers (common in SiGe): give conversion gain, need less LO drive, but have more flicker noise and lower linearity.
• LO distribution to 4 Rx × (I, Q): use a symmetric H-tree or matched LO buffers so that the channel-to-channel phase error is design-matched, not just calibrated. LO leakage into the RF port creates DC offset (self-mixing); the HPF removes it.
• After the mixer: I and Q each need their own IF chain and ADC, matched in gain and group delay, so baseband mismatch adds to the RF quadrature error.

What imbalance does, and how it's corrected

• Rx: the image of each target appears at −f_b. With an up-chirp and complex baseband, real targets sit on positive beat frequencies, so the image mostly falls in the half of the spectrum the processing ignores. The real costs are an image of strong clutter and interference in the negative half, which confuses interference detection and makes it harder to reuse that band. About 25–30 dB IRR analog, plus DFE correction to 40–50 dB, is usually enough.
• Tx rotator: quadrature error there converts directly into phase and amplitude error per code. That is what the LUT in the phase rotator section cancels, so the Tx side is the more demanding user of I/Q accuracy.
• Measurement: the loopback SSB tone at +f_m and its image at −f_m give g and φ in a single capture (see the BIST page).

Echo power falls as R⁻⁴, and range maps linearly to beat frequency. A second-order high-pass filter (+40 dB/decade) therefore flattens the IF spectrum: it attenuates the strong close-in clutter and leakage, so distant echoes use more of the ADC's dynamic range. The VGA then sets the level, and the anti-alias filter bounds noise and aliasing.

Most radar MMICs use continuous-time sigma-delta (CT-ΣΔ) ADCs. Their input is resistive, the anti-aliasing is inherent, and they reach high dynamic range at a modest output rate. Time-interleaved or pipelined SAR ADCs appear where high IF bandwidth matters more (very fast chirps, short range).

• Decimation chain: the ΣΔ modulator runs at a few hundred MHz. CIC and half-band FIR stages bring it down to the programmed output rate and add the final channel filtering.
• DC and I/Q correction: remove static DC offset and apply the gain/phase imbalance coefficients from calibration.
• Interference detection: other radars cross your IF band as short, high-amplitude chirps. Detect them by amplitude or statistics in the time domain, then zero or interpolate the affected samples before the FFT. The alternative is a noise floor raised across the whole chirp.
• Chirp quality flags: saturation, interference and monitor status are written into chirp headers.
• Data path: packed samples go into the on-chip radar cube memory over DMA, or out through CSI-2 / LVDS for raw-data (satellite) architectures that process in a central ECU.

1. Range FFT (per chirp, per Rx, windowed): runs on the fly in the hardware accelerator while the next chirp is being sampled.
2. Doppler FFT (per range bin, across chirps): runs after the frame. Add TDM Doppler compensation or DDMA demultiplexing here.
3. Non-coherent integration and CFAR on the range-Doppler map: CA-CFAR along range, OS-CFAR along Doppler, P_fa ≈ 10⁻⁶. Threshold SNR is about 12–15 dB.
4. Angle estimation for each detected cell: FFT/DBF over the virtual array, or super-resolution (MUSIC, ESPRIT, IAA) for imaging radars. Apply the calibration matrix first.
5. Velocity disambiguation by multi-profile Chinese-remainder methods or by tracking.
6. Point cloud → clustering (DBSCAN) → tracking (EKF/UKF, IMM motion models) → classification. Also ego-motion estimation, and multipath and guardrail suppression.
7. Output: objects and point cloud over CAN-FD (2–5 Mbit/s) or 100/1000BASE-T1 Ethernet.

Compute and memory sizing

The on-chip memory often limits the chirp configuration before the RF does. Compression (block floating point) or processing range bins as they arrive keeps the cube small enough.

A slow SAR auxiliary ADC (10–12 bit, behind an analog mux) reads the power detectors, temperature sensors and supply dividers. Loopback paths inject known signals through the real Rx chain and main ADCs. The RF control CPU runs these monitors in the idle time between frames. The total must fit in the FTTI from the system safety concept.

Deep dive: Radar BIST & Loopback covers stimulus generation, loopback routing, on-chip measurement, trim feedback and instrument-free production test. Digital DFT & stress covers scan, ATPG, memory/logic BIST, burn-in, HVST, PAT and AEC-Q100.

A radar MMIC is a mixed-signal chip with very different loads: a 20 GHz VCO where microvolts of supply noise become FM, PAs that switch hundreds of mA on and off each chirp in TDM, IF and ADC circuits that turn supply ripple directly into IF spurs, and bursty digital FFT loads. The standard answer is efficient bucks off-chip, quiet LDOs on-chip, one LDO per sensitive domain, so that no two noise-sensitive blocks share a regulator.

Circuit-level detail (LDO, bandgap, UV/OV monitors, sequencing, test): power management page.

LDO specification per domain (typical targets)

How supply noise turns into radar errors

• Inside the PLL loop bandwidth (≈ 1–3 MHz) the loop suppresses VCO pushing. Outside it, only the LDO's PSRR helps. Buck converters switch at about 2 MHz, right at that edge, so VCO LDO PSRR at 1–10 MHz is the critical spec.
• TDM Tx switching steps the PA current every chirp. If the LDO hasn't settled when the ADC window opens, each Tx sees a slightly different phase and gain, which looks like a MIMO calibration error that changes with the chirp timing. Size the idle time and the LDO's loop bandwidth together.
• IF/ADC rails: ripple at f_rip appears directly as a tone at f_rip in every chirp: a fixed ghost at the range R = f_rip·c/(2S). Keep buck frequencies out of the used IF band, or sync the buck to the chirp so its harmonics fall in known bins that processing can blank.
• Spread-spectrum bucks trade a clean spur for a raised noise floor, which is often worse for radar than a synchronised, known spur.

LDO design choices

• Low-noise reference: filter the bandgap into the LDO with a large on-chip RC (or a sample-and-hold). The LDO then amplifies its own error-amplifier noise, so size the input pair for low 1/f noise.
• Headroom: 1.8 V → 1.2 V leaves 600 mV for cascoding and high PSRR. 1.0 V → 0.9 V leaves little, so RF LDOs often trade PSRR for dropout, or are bypassed with a clean external 1.0 V.
• Trim and monitoring: a trim DAC sets V_out (eFuse); UV/OV comparators and the aux ADC check each output. The LDO also has current limit and soft-start.
• Sequencing: power-on reset holds the chip until all rails are valid. Enable LDOs in a fixed order (reference → analog → RF) so that no block is biased from a floating rail.

Typical power budget (single chip, 3Tx/4Rx, active frame)

The defaults are a long-range-ish TDM-MIMO configuration. Change a field and every output updates. SNR is after coherent range, Doppler and MIMO integration, minus the lumped losses L (radome, windowing, implementation).

These steps run in order, from the first silicon to the vehicle.

1. Wafer and final test: ATE with a 77 GHz loopback or probe; trim the power detectors, temperature sensors and bandgaps; screen NF, Pout and phase noise.
2. Module EOL: anechoic chamber with a corner reflector (or target simulator) at several angles. Measure Rx/Tx gain and phase mismatch and store the calibration matrix in flash. Measure the antenna pattern and verify EIRP.
3. Runtime calibration: temperature-indexed LUTs for Tx power and phase, and monitor-driven recalibration.
4. Mounting alignment: EOL alignment on the vehicle, plus online auto-alignment from stationary targets and ego-motion.
5. Radar target simulator (RTS) HIL: scenario and interference tests, ghost and multipath checks.
6. Compliance: ETSI EN 301 091 / EN 303 396 or FCC Part 95M (EIRP, OOB, spurious); EMC; ISO 26262 safety case; cybersecurity (ISO/SAE 21434) for the SW and interfaces.

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