Knowledge Graph

Knowledge graph: how circuits, parameters and tests connect

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A map of the key items on every page and how they depend on each other, like a graph view of a personal knowledge base. It has 141 items and 295 connections. Click an item to see what it connects to and why, open the section that explains it, and see the other sections that mention it. Use the type buttons to hide groups, and Focus to show only the neighbourhood of the selected item.

Drag to pan · wheel or pinch to zoom · drag an item to move it · click for details

How to read it: an arrow reads as a sentence from its start to its end, for example LNA → dominates → Noise figure. A bigger item has more connections. Each type has its own shape as well as its colour, so the groups stay clear in print and for colour-blind readers.

All items as a table

Item	Type	What it is
Antenna	Circuit	Tx and Rx antennas and the chip-to-antenna transition; its loss adds straight to the noise figure and subtracts from Tx power.
PA	Circuit	Power amplifier: drives the chirp into the Tx antenna through a transformer balun.
LNA	Circuit	Low-noise amplifier: first gain stage of the receiver; its noise and gain set the receiver noise figure.
Mixer + TIA	Circuit	Passive double-balanced mixer with a transimpedance amplifier: multiplies the echo by the LO to give the IF beat signal.
IF filter / HPF	Circuit	High-pass and anti-alias filters in the IF chain: suppress close-in leakage and set the IF band before the ADC.
VGA / PGA	Circuit	Programmable IF gain amplifier with switched feedback resistors; sets the signal level for the ADC.
ADC	Circuit	Converts the IF beat signal to digital; also used by BIST to measure on-chip detectors.
DFE	Circuit	Digital front end: decimation, filtering and data formatting before the radar processing.
Radar DSP (FFT)	Circuit	Range and Doppler FFTs, CFAR detection and angle estimation.
Phase rotator	Circuit	Sets the phase of each Tx channel for beam steering and MIMO coding; built from I/Q vector summing.
Rotator DAC	Circuit	Current DACs that weight the I and Q vectors of the phase rotator; their INL/DNL and bow set phase accuracy.
Power detector	Circuit	Diode or square-law detector on the Tx output coupler; its DC output tells the chip the Tx power.
PFD + charge pump	Circuit	Phase-frequency detector and charge pump: compare reference and divided VCO and pump current into the loop filter.
Loop filter	Circuit	RC network that turns charge-pump current into the VCO tuning voltage and sets loop bandwidth and stability.
VCO	Circuit	LC-tank voltage-controlled oscillator (about 19–20 GHz, then ×4) with switched-capacitor sub-bands.
Divider / ΣΔ	Circuit	Multi-modulus divider driven by a sigma-delta modulator for fractional-N division.
Ramp generator	Circuit	Digital chirp generator that steps the fractional divide ratio to sweep the frequency.
×4 multiplier	Circuit	Frequency multiplier from the VCO band to 76–81 GHz.
LO distribution	Circuit	Buffers and lines that carry the 77 GHz LO to every Tx rotator and Rx mixer.
LDO	Circuit	Low-dropout regulators that give each block a clean, local supply.
Bandgap	Circuit	Temperature-stable voltage reference for LDOs, monitors, ADC and bias currents.
UV / OV monitor	Circuit	Window comparators that flag under- and over-voltage on each supply for functional safety.
POR & sequencing	Circuit	Power-on reset and the order in which supplies, references and clocks come up.
ESD diodes	Circuit	Protection diodes on every pin; open/short test forward-biases them to check continuity.
Scan chains	Circuit	Flip-flops linked into shift registers so the digital logic can be controlled and observed by the tester.
Memory BIST	Circuit	On-chip March-algorithm tester for the radar data memories.
Logic BIST	Circuit	Pseudo-random self-test of the logic, also run in the field at key-on.
JTAG / IJTAG	Circuit	Test access port and instrument network that reach scan, BIST and trim registers.
Test mux / ATB	Circuit	Analog test muxes and the analog test bus: connect each sub-block node to the aux ADC, main ADC or a test pin.
Loopback switches	Circuit	RF SP4T switches and splitter that choose which Tx feeds which Rx in the loopback.
Digital test muxes	Circuit	Scan, clock, reset, bypass and pin-sharing muxes that test mode controls.
BIST controller	Circuit	On-chip sequencer that sets up loopback paths, runs measurements and compares results with limits.
Noise figure	Parameter	How much noise the receiver adds; set mostly by input loss and the LNA (Friis).
Rx gain	Parameter	Total receive-chain gain from antenna to ADC; high LNA gain hides later noise.
IIP3 / P1dB	Parameter	Linearity of the receive chain; late stages (mixer, VGA) usually limit it.
Tx output power	Parameter	Power at the Tx ball, typically 10–14 dBm per channel.
PAE	Parameter	Power-added efficiency of the PA; sets heat and supply current.
Phase noise	Parameter	Noise on the LO phase; limits detection of weak targets next to strong ones.
Chirp linearity	Parameter	How straight the frequency ramp is; nonlinearity smears range peaks.
Lock time / lock detect	Parameter	How fast the PLL settles and how the chip knows it is locked.
KVCO / tuning range	Parameter	VCO gain (MHz/V) and the frequency span of each sub-band.
I/Q imbalance	Parameter	Gain and phase mismatch between I and Q paths; creates image (ghost) targets.
ADC SNR / ENOB	Parameter	Effective resolution of the ADC; sets the dynamic range at the digital side.
DAC INL / DNL	Parameter	Linearity of the rotator DACs; bow (2nd-order INL) becomes phase and amplitude error.
PSRR	Parameter	How well a regulator or circuit rejects supply noise; poor PSRR shows up as spurs.
Dropout / load regulation	Parameter	Minimum headroom across the LDO and its output change with load current.
Vth	Parameter	Transistor threshold voltage; shifts speed, bias points and leakage.
fT / fmax	Parameter	Transistor cut-off and maximum oscillation frequencies; set the headroom at 77 GHz.
gm / Idsat	Parameter	Transconductance and saturation current: the drive strength of the transistor.
Ioff / leakage	Parameter	Off-state transistor current; sets standby and IDDQ baseline.
Breakdown voltage	Parameter	Junction, oxide and drain breakdown limits; cap PA swing and stress-test levels.
Sheet R / matching	Parameter	Resistor and capacitor values and their matching; set gain steps, filter corners and trim range.
Contact resistance	Parameter	Probe or socket contact resistance; drifts as needles wear and falsely fails parametric tests.
Max range / SNR	Parameter	Detection range from the radar equation: Tx power, antenna gain, NF and integration time.
Range resolution	Parameter	c / 2B: set by the chirp bandwidth.
Cpk	Parameter	Process capability: distance from the mean to the nearest limit in units of 3σ.
Open / short test	Test	Forces current into each pin through its ESD diode to find opens and shorts before any other test.
Walking-Z	Test	Tri-states pins one at a time to find pin-to-pin shorts and leakage.
IDDQ	Test	Quiescent supply current in several scan states; a raised value reveals bridges and gate-oxide defects.
At-speed test	Test	Transition and path-delay scan patterns at the functional clock to catch slow paths.
HVST / burn-in	Test	High-voltage stress and burn-in accelerate weak oxide and metal defects to failure before shipment.
VLV / Vmin	Test	Very-low-voltage test: runs logic and memory below nominal supply to expose marginal cells and resistive defects.
RF loopback	Test	Routes the Tx signal back into the Rx on-chip so the whole RF path is tested without mmWave instruments.
On-chip measurement	Test	Detectors, counters and the ADC measure power, frequency, gain and phase inside the chip (BISM).
Trim & calibration	Test	Measured errors are written back as trim codes: bandgap, LDO, VCO band, I/Q, phase, gain.
PCM / WAT	Test	Scribe-line test structures measured on every wafer before sort: Vth, Idsat, leakage, sheet R, breakdown.
SPC	Test	Control charts and run rules that keep each WAT parameter in control.
PAT / GDBN	Test	Outlier screens: part-average testing and good-die-in-bad-neighbourhood removal for zero-defect automotive.
AEC-Q100	Test	Automotive qualification: HTOL, temperature cycling, ESD, latch-up and more.
Production test flow	Test	The order of test insertions from wafer sort to final test and system test.
Fail bins	Test	Where each failing die is sorted; bin data drives yield analysis.
Corners & mismatch	Fab & package	Process corners (SS/FF/SF/FS) and local mismatch that designs must survive.
Wafer map signature	Fab & package	Spatial patterns of failing die that point to a process tool or setting.
CMP	Fab & package	Chemical-mechanical polishing: centre/edge rings from pad wear, slurry or pressure zones.
Reticle / litho	Fab & package	Exposure and reticle issues that repeat in every shot on the wafer.
Fan-out (eWLB)	Fab & package	Fan-out wafer-level package common for 77 GHz radar: low-loss RDL, no bond wires.
Antenna in package	Fab & package	Antennas built into the package, removing the PCB RF launch.
RDL	Fab & package	Redistribution layers that route die pads to balls and carry the mmWave transitions.
Bump / ball	Fab & package	Solder bumps and balls: pitch, height and under-bump metallurgy.
Solder fatigue	Fab & package	Thermal cycling cracks the solder joints; the leading package failure in automotive.
Temperature cycling	Fab & package	Cycling −40/+125 °C (or −55/+150 °C) accelerates fatigue and delamination.
Anti-alias filter	Circuit	Low-pass filter before the ADC that stops signals near fs from folding into the band; relaxed with a CT-ΣΔ ADC.
Decimation filter	Circuit	CIC and half-band FIR stages that turn the ΣΔ bit stream into 16-bit samples at 2× the IF bandwidth.
Embedded SRAM	Circuit	6T-cell SRAM macros for radar cube, DSP and CPU; densest structure on the die.
Memory faults / bitmap	Fab & package	Stuck-at, coupling, retention and disturb faults; their bitmap shape points to the process cause.
Redundancy & repair	Test	Spare rows and columns allocated by BIRA and stored in fuses.
Soft errors / ECC	Fab & package	Particle-induced bit flips corrected by SEC-DED ECC and scrubbing.
Package qualification	Test	AEC-Q100 stress tests of the packaged chip: preconditioning, TC, HAST/THB, autoclave, HTSL, HTOL, with read-points and pass criteria.
Cross-section / DPA	Test	Physical analysis after stress: CSAM, X-ray, cross-sections, SEM/EDX and shear tests.
Assembly flow	Fab & package	Bumping, dicing, fan-out molding, RDL build-up, ball attach and singulation.
Die shift / warpage	Fab & package	Die movement during molding and package bending at reflow; cause RDL misalignment and open joints.
Bench bring-up	Test	Step-by-step first-silicon test on the evaluation board, from continuity to system test.
OTA / chamber test	Test	Over-the-air measurement in an anechoic chamber with reflectors and target simulators.
Radome / bumper	Fab & package	Plastic cover in front of the antennas; its thickness and paint set loss and reflections.
Module EOL calibration	Test	Antenna gain and phase calibration and boresight alignment of the finished module.
Junction temperature	Parameter	Die temperature set by power and the thermal path; drives RF performance and aging.
Power delivery / PI	Circuit	Regulators, planes and decoupling; supply noise here becomes LO spurs.
EMC tests	Test	CISPR 25 emissions and ISO 11452 immunity tests of the module.
EM / post-layout simulation	Test	Electromagnetic models and parasitic extraction that predict mmWave performance before tape-out.
Test cost	Parameter	Cost per good die from tester rate, test time, sites and yield.
eFuse / OTP	Circuit	One-time-programmable bits (poly eFuse, antifuse) that store trim codes, die ID and repair for life.
Shadow registers	Circuit	Registers loaded from the fuses at boot; they drive the trim DACs and allow soft trim during test.
ACC	System	Adaptive cruise control: keeps a time gap to the car ahead using the front long-range radar.
AEB	System	Automatic emergency braking for cars, pedestrians and cyclists, from time-to-collision.
BSD / LCA	System	Blind-spot detection and lane-change assist from the rear corner radars.
RCTA / RCTB	System	Rear cross-traffic alert and braking when reversing.
4D imaging radar	System	High-channel radar that also measures elevation, for L2+ and L3 driving.
Saturation detector	Circuit	Window comparators, peak detectors and ADC over-range flags that report clipping in each receive stage.
Clock jitter	Parameter	Timing noise of the ADC clock; limits SNR at high IF frequencies.
Radar cube memory	Circuit	On-chip SRAM holding range × chirp × channel data for the Doppler and angle processing.
CFAR detection	System	Adaptive threshold that finds targets at a constant false-alarm rate.
Angle estimation	System	Direction of arrival over the virtual array: FFT beamforming or super-resolution.
Data interface	Circuit	CSI-2, automotive Ethernet, SPI or CAN-FD link to the host.
FTTI	Parameter	Fault-tolerant time interval: detection and reaction must finish within it.
SPFM / LFM / PMHF	Parameter	ISO 26262 hardware metrics that the FMEDA must meet for the ASIL.
Key-on tests	Test	Start-up self-tests of logic, memories and the monitors themselves, for latent faults.
ESD power clamp	Circuit	RC-triggered large NMOS between supply rails that carries the ESD current.
HBM / CDM	Test	ESD qualification stresses: human-body and charged-device models.
Latch-up	Fab & package	Parasitic thyristor turning on and shorting the supplies.
HCI	Fab & package	Hot-carrier injection: drain-side damage that lowers gain and output power over life.
NBTI / PBTI	Fab & package	Threshold shift under gate bias at high temperature; slows logic and shifts analog bias.
TDDB	Fab & package	Time-dependent gate-oxide breakdown.
Electromigration	Fab & package	Metal atoms pushed by current density; opens and shorts in supply lines.
HTOL / FIT	Test	High-temperature operating life test and the failure rate derived from it.
Mission profile	System	15-year temperature, voltage and on-time profile that sets the aging and FIT budget.
Guard band / test limits	Parameter	Margin between spec and test limit for measurement error, temperature and aging.
Lab–ATE correlation	Test	Golden units measured in the lab and on the tester to align production results.
Gage R&R	Test	Repeatability and reproducibility of the measurement system.
Die yield (D0)	Parameter	Share of good dies, set by defect density and area plus parametric margin.
DPPM / escapes	Parameter	Defective parts per million that pass test; automotive goal below 1.
SYL / SBL	Test	Statistical yield and bin limits that hold abnormal lots.
Failure analysis / 8D	Test	Root-cause analysis of returns and the 8D corrective-action process.
EIRP / band limits	Parameter	Regulatory power and band-edge limits in each market.
Radar interference	System	Other radars crossing the chirp; raises the noise floor or creates ghosts.
FMCW chirp	System	A linear frequency ramp; the beat frequency between Tx and echo gives range.
Beam steering / MIMO	System	Tx phases steer the beam or code the channels so the receiver can separate them (virtual array).
Tx power loop	System	Detector, ADC and digital control that hold the Tx power constant over temperature and ageing.
AGC	System	Automatic gain control: picks the VGA gain so strong echoes do not clip the ADC.
Supply tree	System	Battery or PMIC rails split into domains and local LDOs.
Functional safety	System	ISO 26262 / ASIL: in-field monitors and self-tests that detect faults within the fault-tolerant time.
Digital timing	System	Setup and hold margins of the logic; corners and mismatch can break them.

All connections as a table

From	Relation	To
Antenna	feeds the echo to	LNA
LNA	amplifies into	Mixer + TIA
Mixer + TIA	IF output to	IF filter / HPF
IF filter / HPF	filters for	VGA / PGA
VGA / PGA	sets the level for	ADC
ADC	samples for	DFE
DFE	decimates for	Radar DSP (FFT)
VCO	output is multiplied by	×4 multiplier
×4 multiplier	drives	LO distribution
LO distribution	LO for	Mixer + TIA
LO distribution	LO for	Phase rotator
Phase rotator	drives	PA
PA	radiates through	Antenna
Rotator DAC	sets the phase of	Phase rotator
Phase rotator	enables	Beam steering / MIMO
PA	is sampled by	Power detector
Power detector	feeds	Tx power loop
Tx power loop	adjusts the drive of	PA
Tx power loop	regulates	Tx output power
Power detector	is read by	ADC
Ramp generator	modulates	Divider / ΣΔ
Divider / ΣΔ	feeds back to	PFD + charge pump
PFD + charge pump	pumps charge into	Loop filter
Loop filter	tunes	VCO
VCO	is divided by	Divider / ΣΔ
FMCW chirp	is generated by	Ramp generator
LNA	dominates	Noise figure
LNA	sets most of	Rx gain
Mixer + TIA	contributes to	IIP3 / P1dB
VGA / PGA	often limits	IIP3 / P1dB
Mixer + TIA	mismatch causes	I/Q imbalance
LO distribution	quadrature error causes	I/Q imbalance
ADC	is rated by	ADC SNR / ENOB
Rotator DAC	is limited by	DAC INL / DNL
PA	sets	Tx output power
PA	is rated by	PAE
VCO	sets far-out	Phase noise
Loop filter	bandwidth sets close-in	Phase noise
Loop filter	bandwidth sets	Lock time / lock detect
Loop filter	bandwidth limits	Chirp linearity
VCO	is characterised by	KVCO / tuning range
Ramp generator	determines	Chirp linearity
LDO	is rated by	PSRR
LDO	is rated by	Dropout / load regulation
Noise figure	limits	Max range / SNR
Tx output power	sets	Max range / SNR
Antenna	loss reduces	Max range / SNR
Phase noise	masks weak targets, limiting	Max range / SNR
FMCW chirp	bandwidth sets	Range resolution
Chirp linearity	smears peaks, degrading	Range resolution
I/Q imbalance	creates ghost targets in	Radar DSP (FFT)
DAC INL / DNL	becomes phase error in	Beam steering / MIMO
ADC SNR / ENOB	limits dynamic range of	Max range / SNR
AGC	controls	VGA / PGA
AGC	prevents clipping in	ADC
IIP3 / P1dB	decides when strong echoes need	AGC
IF filter / HPF	removes close-in leakage before	AGC
fT / fmax	limits gain and noise of	LNA
fT / fmax	limits output power of	PA
fT / fmax	limits tuning of	VCO
fT / fmax	sets the floor of	Noise figure
gm / Idsat	with Cgs sets	fT / fmax
Vth	shifts	gm / Idsat
Vth	is spread by	Corners & mismatch
Corners & mismatch	shifts the band of	KVCO / tuning range
Corners & mismatch	can break	Digital timing
Corners & mismatch	shifts	I/Q imbalance
Ioff / leakage	sets the baseline of	IDDQ
Ioff / leakage	rises at FF corner in	Corners & mismatch
Sheet R / matching	sets gain steps of	VGA / PGA
Sheet R / matching	sets trim range of	Bandgap
Sheet R / matching	sets corners of	IF filter / HPF
Sheet R / matching	mismatch limits	DAC INL / DNL
Breakdown voltage	caps the swing of	PA
Breakdown voltage	sets the level of	HVST / burn-in
PCM / WAT	measures	Vth
PCM / WAT	measures	Ioff / leakage
PCM / WAT	measures	gm / Idsat
PCM / WAT	measures	Sheet R / matching
PCM / WAT	measures	Breakdown voltage
PCM / WAT	is modelled for	fT / fmax
PCM / WAT	is monitored by	SPC
SPC	reports capability as	Cpk
PCM / WAT	correlates with	Wafer map signature
CMP	makes rings in	Wafer map signature
Reticle / litho	makes repeats in	Wafer map signature
CMP	thickness shifts	Sheet R / matching
Reticle / litho	CD shifts	Vth
Wafer map signature	feeds	PAT / GDBN
Production test flow	starts after	PCM / WAT
Supply tree	branches into	LDO
Bandgap	is the reference for	LDO
Bandgap	sets thresholds of	UV / OV monitor
UV / OV monitor	reports faults to	Functional safety
POR & sequencing	sequences	LDO
POR & sequencing	waits for	Bandgap
LDO	supplies	VCO
LDO	supplies	PA
LDO	supplies	LNA
PSRR	supply noise becomes spurs in	Phase noise
Dropout / load regulation	limits headroom of	PA
UV / OV monitor	watches	Supply tree
BIST controller	sets up	RF loopback
BIST controller	runs	On-chip measurement
RF loopback	tests the Rx path of	LNA
RF loopback	tests the Tx path of	PA
RF loopback	checks	I/Q imbalance
On-chip measurement	uses	Power detector
On-chip measurement	measures with	ADC
On-chip measurement	counts the frequency of	VCO
On-chip measurement	result drives	Trim & calibration
Trim & calibration	calibrates	Rotator DAC
Trim & calibration	corrects	I/Q imbalance
Trim & calibration	trims	Bandgap
Trim & calibration	selects the sub-band of	VCO
On-chip measurement	checks	Lock time / lock detect
BIST controller	provides in-field monitoring for	Functional safety
Logic BIST	provides in-field test for	Functional safety
Memory BIST	provides in-field test for	Functional safety
JTAG / IJTAG	controls	BIST controller
Tx power loop	is checked by	On-chip measurement
IF filter / HPF	feeds	Anti-alias filter
Anti-alias filter	protects	ADC
ADC	streams into	Decimation filter
Decimation filter	hands samples to	DFE
Clock jitter	limits	ADC SNR / ENOB
Sheet R / matching	sets corners of	Anti-alias filter
Radar DSP (FFT)	reads and writes	Radar cube memory
Memory BIST	tests	Radar cube memory
Radar DSP (FFT)	runs	CFAR detection
Radar DSP (FFT)	runs	Angle estimation
CFAR detection	sets the false-alarm rate for	Max range / SNR
Angle estimation	relies on channel calibration of	Beam steering / MIMO
Radar DSP (FFT)	sends the point cloud through	Data interface
Functional safety	must react within	FTTI
Functional safety	is proven by	SPFM / LFM / PMHF
Key-on tests	finds latent faults for	SPFM / LFM / PMHF
Logic BIST	runs as part of	Key-on tests
UV / OV monitor	is self-tested by	Key-on tests
ESD diodes	discharges through	ESD power clamp
HBM / CDM	stresses	ESD power clamp
Breakdown voltage	sets the design window of	ESD power clamp
HBM / CDM	is part of	AEC-Q100
Latch-up	is tested in	AEC-Q100
ESD diodes	adds capacitance to the match of	LNA
HCI	lowers the power of	PA
NBTI / PBTI	shifts	VCO
NBTI / PBTI	slows	Digital timing
TDDB	shows up in	IDDQ
Electromigration	limits current in	LDO
HTOL / FIT	accelerates	HCI
HTOL / FIT	accelerates	NBTI / PBTI
Mission profile	sets the stress of	HTOL / FIT
HTOL / FIT	is part of	AEC-Q100
Breakdown voltage	sets the TDDB margin for	TDDB
Guard band / test limits	protects	DPPM / escapes
Lab–ATE correlation	sets the uncertainty in	Guard band / test limits
Gage R&R	feeds	Guard band / test limits
Guard band / test limits	uses the spread from	Cpk
On-chip measurement	is aligned to the lab by	Lab–ATE correlation
Die yield (D0)	is lost in	Fail bins
Wafer map signature	explains	Die yield (D0)
PAT / GDBN	reduces	DPPM / escapes
SYL / SBL	holds lots flagged by	Fail bins
Failure analysis / 8D	feeds corrective action into	Production test flow
DPPM / escapes	is investigated by	Failure analysis / 8D
EIRP / band limits	caps	Tx output power
Chirp linearity	keeps the chirp inside	EIRP / band limits
Radar interference	raises the noise floor for	CFAR detection
Radar interference	is detected in	DFE
Ramp generator	randomises chirps against	Radar interference
Embedded SRAM	stores	Radar cube memory
Memory BIST	tests	Embedded SRAM
Memory BIST	produces	Memory faults / bitmap
Vth	mismatch limits Vmin of	Embedded SRAM
Memory faults / bitmap	is repaired by	Redundancy & repair
Redundancy & repair	stores addresses in	eFuse / OTP
Wafer map signature	is overlaid with	Memory faults / bitmap
VLV / Vmin	finds weak cells in	Embedded SRAM
Soft errors / ECC	flips bits in	Embedded SRAM
Soft errors / ECC	counts toward	SPFM / LFM / PMHF
NBTI / PBTI	raises Vmin of	Embedded SRAM
Package qualification	is part of	AEC-Q100
Package qualification	includes	Temperature cycling
Package qualification	includes	HTOL / FIT
Mission profile	sets the conditions of	Package qualification
Package qualification	is inspected by	Cross-section / DPA
Cross-section / DPA	finds cracks in	Solder fatigue
Cross-section / DPA	checks	RDL
Cross-section / DPA	feeds	Failure analysis / 8D
Assembly flow	is qualified by	Package qualification
Assembly flow	builds	Fan-out (eWLB)
Assembly flow	patterns	RDL
Assembly flow	forms	Bump / ball
Assembly flow	takes known-good dies from	Production test flow
Die shift / warpage	misaligns	RDL
Die shift / warpage	causes opens found by	Open / short test
Die shift / warpage	leads to	Solder fatigue
EM / post-layout simulation	sets the line widths of	Assembly flow
Bench bring-up	creates reference data for	Lab–ATE correlation
Bench bring-up	checks first	Open / short test
OTA / chamber test	measures	Antenna
OTA / chamber test	verifies	Max range / SNR
Radome / bumper	adds loss in front of	Antenna
Module EOL calibration	calibrates	Beam steering / MIMO
Module EOL calibration	is done through	OTA / chamber test
Radome / bumper	is corrected by	Module EOL calibration
Junction temperature	lowers	Tx output power
Junction temperature	accelerates	HTOL / FIT
Junction temperature	is read by	On-chip measurement
Mission profile	sets the profile of	Junction temperature
Power delivery / PI	feeds	LDO
PSRR	protects the LO from	Power delivery / PI
Power delivery / PI	noise causes spurs in	Phase noise
EMC tests	tests the module for	Functional safety
EM / post-layout simulation	predicts	fT / fmax
EM / post-layout simulation	models the transition of	RDL
EM / post-layout simulation	is compared with	Bench bring-up
Test cost	is cut by	On-chip measurement
Test cost	depends on	Die yield (D0)
Production test flow	sets the insertions in	Test cost
Trim & calibration	stores codes in	eFuse / OTP
eFuse / OTP	loads at boot into	Shadow registers
Shadow registers	sets	Bandgap
Shadow registers	sets	LDO
Electromigration	is the mechanism that programs	eFuse / OTP
TDDB	is the mechanism of antifuse	eFuse / OTP
Key-on tests	checks the CRC of	eFuse / OTP
Memory BIST	stores repair addresses in	eFuse / OTP
HTOL / FIT	qualifies retention of	eFuse / OTP
ACC	needs long	Max range / SNR
ACC	assigns lanes with	Angle estimation
AEB	must react within	FTTI
AEB	needs fine	Range resolution
AEB	detects with	CFAR detection
BSD / LCA	needs wide-FoV	Antenna
RCTA / RCTB	needs wide-angle	Angle estimation
4D imaging radar	needs many channels for	Beam steering / MIMO
4D imaging radar	streams data through	Data interface
Radar interference	degrades	AEB
Functional safety	covers	AEB
Saturation detector	protects pedestrian detection in	AEB
Saturation detector	flags clipping in	ADC
Saturation detector	watches the output of	VGA / PGA
Saturation detector	tells	AGC
Saturation detector	reports a blind receiver to	Functional safety
Radar interference	trips	Saturation detector
Key-on tests	self-tests	Saturation detector
IIP3 / P1dB	sets the level that trips	Saturation detector
BIST controller	sets the selects of	Test mux / ATB
Test mux / ATB	brings nodes to	ADC
Test mux / ATB	reads	Bandgap
Test mux / ATB	reads	LDO
Test mux / ATB	reads the tuning voltage of	VCO
Test mux / ATB	reads	Power detector
Test mux / ATB	copies the bias current of	LNA
Ioff / leakage	leakage limits the accuracy of	Test mux / ATB
Test mux / ATB	is locked off in the field for	Functional safety
On-chip measurement	is routed by	Test mux / ATB
RF loopback	is routed by	Loopback switches
Loopback switches	taps the output of	PA
Digital test muxes	builds	Scan chains
Digital test muxes	switches the test clocks for	At-speed test
Digital test muxes	brings out	Lock time / lock detect
JTAG / IJTAG	sets	Digital test muxes
JTAG / IJTAG	accesses	Scan chains
Scan chains	tests the logic for	Digital timing
At-speed test	uses	Scan chains
At-speed test	catches slow paths in	Digital timing
IDDQ	uses scan states from	Scan chains
VLV / Vmin	finds marginal	Digital timing
HVST / burn-in	is followed by	PAT / GDBN
Logic BIST	reuses	Scan chains
HVST / burn-in	accelerates oxide defects seen by	IDDQ
Open / short test	forward-biases	ESD diodes
Walking-Z	extends	Open / short test
Open / short test	is guarded by	Contact resistance
Open / short test	finds opens in	Bump / ball
Production test flow	begins with	Open / short test
Production test flow	runs	Scan chains
Production test flow	runs	RF loopback
Production test flow	sorts dies into	Fail bins
Production test flow	includes	HVST / burn-in
PAT / GDBN	moves outliers into	Fail bins
Contact resistance	is logged per	Fail bins
Fan-out (eWLB)	routes through	RDL
RDL	connects to	Bump / ball
Bump / ball	fails by	Solder fatigue
Temperature cycling	accelerates	Solder fatigue
Antenna in package	integrates	Antenna
Antenna in package	is built on	Fan-out (eWLB)
RDL	transition loss reduces	Max range / SNR
AEC-Q100	includes	Temperature cycling
AEC-Q100	includes	HVST / burn-in
Fan-out (eWLB)	is qualified by	AEC-Q100

Glossary of abbreviations

Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.

Radar system & ADAS

Abbr.	Stands for	Note
FCW	Forward Collision Warning	Warns of an imminent frontal collision; stage before AEB.
FCTA	Front Cross-Traffic Alert	Front corner-radar function at junctions and driveways.
RCTB	Rear Cross-Traffic Braking	Brakes automatically when RCTA detects cross traffic while reversing.
DOW	Door-Opening Warning	Warns before a door is opened into an approaching cyclist or car.
VRU	Vulnerable Road User	Pedestrians, cyclists and motorcyclists.
TTC	Time To Collision	Range divided by closing speed; triggers warnings and braking.
LRR	Long-Range Radar	Front radar, ≈ 200–300 m, narrow field of view.
MRR	Mid-Range Radar	≈ 80–160 m, ±40–60° field of view.
SRR	Short-Range Radar	Corner radar, ≈ 30–80 m, ±75–90° field of view.
NCAP	New Car Assessment Programme	Consumer safety ratings (Euro NCAP, C-NCAP, IIHS …).
GSR	General Safety Regulation (EU) 2019/2144	Makes AEB and other assistance functions mandatory in the EU.
CPD	Child Presence Detection	In-cabin sensing (often 60 GHz radar) that detects a child left in the car.
ACC	Adaptive Cruise Control	Keeps distance to the car ahead; uses long-range front radar.
ADAS	Advanced Driver-Assistance Systems	The vehicle functions the radar serves.
AEB	Autonomous Emergency Braking	Brakes automatically when a collision is imminent.
BSD	Blind-Spot Detection	Corner-radar function.
LCA	Lane-Change Assist	Corner-radar function that warns of fast approaching vehicles.
RCTA	Rear Cross-Traffic Alert	Rear corner-radar function when reversing.
L2	SAE automation Level 2 (L3 = Level 3)	Partial (L2) and conditional (L3) driving automation.
FMCW	Frequency-Modulated Continuous Wave	A linear chirp; range comes from the beat frequency f_b = S·2R/c.
FoV	Field of View	Angular coverage in azimuth and elevation.
RCS	Radar Cross Section	Target reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0).
dBsm	Decibels relative to 1 m²	Unit of RCS.
EIRP	Effective Isotropic Radiated Power	Tx power + antenna gain; limited by regulations.
MIMO	Multiple-Input Multiple-Output	N_tx × N_rx channels form a larger virtual array.
TDM	Time-Division Multiplexing	One Tx per chirp; v_max falls by a factor of N_tx.
BPM	Binary Phase Modulation	0/180° codes across chirps separate the Tx signals.
DDMA	Doppler-Division Multiple Access	Each Tx gets a slow-time phase ramp and separates in Doppler.
DoA	Direction of Arrival	Angle estimation over the virtual array.
DBF	Digital Beamforming	FFT or matched steering over array channels.
CFAR	Constant False Alarm Rate	Adaptive detection threshold (CA = cell-averaging, OS = ordered-statistic).
FFT	Fast Fourier Transform	Range, Doppler and angle FFTs build the radar cube.
SNR	Signal-to-Noise Ratio
MUSIC	MUltiple SIgnal Classification	Subspace super-resolution DoA algorithm.
ESPRIT	Estimation of Signal Parameters via Rotational Invariance Techniques	Super-resolution DoA algorithm.
IAA	Iterative Adaptive Approach	Super-resolution spectral / DoA estimator.
DBSCAN	Density-Based Spatial Clustering of Applications with Noise	Groups detections into objects.
EKF	Extended Kalman Filter	Nonlinear tracking filter.
UKF	Unscented Kalman Filter	Nonlinear tracking filter using sigma points.
IMM	Interacting Multiple Model	Tracker that mixes several motion models.
HWA	Hardware Accelerator	On-chip FFT / radar processing engine.
RTS	Radar Target Simulator	Echo generator for HIL and EOL testing.
HIL	Hardware-in-the-Loop	Testing the real sensor against simulated scenarios.
EOL	End-of-Line	Final production test of a module or vehicle.

RF & analog front end

Abbr.	Stands for	Note
HPBW	Half-Power Beamwidth	Angle between the −3 dB points of an antenna or array beam.
PDN	Power Delivery Network	Regulators, planes, decoupling and package paths that supply the chip.
PI	Power Integrity	Keeping supply voltage within limits under load steps and noise.
EMI	Electromagnetic Interference	Unwanted emission or pick-up of electromagnetic energy.
BCI	Bulk Current Injection	Immunity test (ISO 11452-4) that injects RF current into a cable harness.
TIM	Thermal Interface Material	Gap pad or paste between board or package and the heat sink.
RF	Radio Frequency	Here the 76–81 GHz signal.
LO	Local Oscillator	The chirp signal that drives the Tx and the Rx mixers.
IF	Intermediate Frequency	The beat / baseband signal after the mixer, DC–20 MHz.
PA	Power Amplifier	Tx output stage, 12–14 dBm.
LNA	Low-Noise Amplifier	First Rx stage; sets most of the NF.
NF	Noise Figure	Noise the receiver adds, in dB.
VGA	Variable-Gain Amplifier	Programmable-gain stage (IF), or signed VGAs in the phase rotator.
TIA	Transimpedance Amplifier	Current-to-voltage stage after a passive mixer.
HPF	High-Pass Filter	In IF: removes leakage and DC, and equalises R⁻⁴.
LPF	Low-Pass Filter
AAF	Anti-Aliasing Filter	Low-pass filter in front of the ADC.
PPF	Polyphase Filter	RC-CR network that generates I/Q.
I/Q	In-phase / Quadrature	Two copies of a signal 90° apart.
IRR	Image Rejection Ratio	How well an I/Q path suppresses the mirror frequency.
SSB	Single Sideband	A frequency shift in one direction only, e.g. the loopback offset.
BPSK	Binary Phase-Shift Keying	0/180° switching; produces ±f_m sidebands.
VM	Vector Modulator	I/Q-weighted phase rotator.
RTPS	Reflection-Type Phase Shifter	Hybrid coupler terminated by tunable loads.
P1dB	1 dB compression point	Input (or output) level where gain drops by 1 dB.
IIP3	Input third-order intercept point	Linearity figure; cascades with the gain before each stage.
PAE	Power-Added Efficiency	(P_out − P_in) / P_DC of a PA.
Psat	Saturated output power	Maximum output power of a PA.
DSB	Double Sideband	Noise figure counting both sidebands (typical for zero-IF mixers).
PGA	Programmable-Gain Amplifier	IF VGA with digitally set gain steps.
AGC	Automatic Gain Control	Loop that sets the VGA gain from the signal level.
HD2	2nd-order Harmonic Distortion (HD3 = 3rd)	Harmonics show up as ghost targets at 2×/3× range.
AM/PM	Amplitude-to-phase conversion	Phase change caused by amplitude or supply changes.
RL	Return Loss	Match quality, in dB.
Cpl	Coupler (directional coupler)	Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback.
PD	Power Detector	Diode or square-law RF-to-DC converter.
APC	Automatic Power Control	Closed loop from the power detector to the VGA/PA gain code.
DPD	Digital Predistortion	Wideband PA linearisation used in comms; radar uses static gain/phase LUTs instead.
VSWR	Voltage Standing-Wave Ratio	Mismatch at the antenna/load; changes the delivered power.
CW	Continuous Wave	An unmodulated single-frequency tone.
ENR	Excess Noise Ratio	Calibrated output level of a noise source.
SiGe	Silicon-Germanium (BiCMOS)	Bipolar-plus-CMOS process used for earlier radar chips.
CMOS	Complementary Metal-Oxide-Semiconductor	RFCMOS = CMOS process with RF / mmWave capability.
RFCMOS	RF-capable CMOS	Today's single-chip radar process (e.g. 45/40/28/22 nm).
NMOS	N-channel MOS transistor (PMOS = P-channel)
PTAT	Proportional To Absolute Temperature	Voltage or current used by temperature sensors.
BG	Bandgap reference	Temperature-stable voltage reference (BG1/BG2 = two independent ones).
PVT	Process, Voltage, Temperature	Variation corners a design must cover.

LO, clock & synthesis

Abbr.	Stands for	Note
PLL	Phase-Locked Loop	Locks the VCO to the crystal and generates the ramp.
ADPLL	All-Digital PLL	PLL with a TDC and a digital loop filter.
VCO	Voltage-Controlled Oscillator	≈ 19–20.25 GHz, multiplied ×4 to 77 GHz.
PFD	Phase-Frequency Detector	Compares the divided VCO with the reference.
CP	Charge Pump; also Chip Probe	In a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test.
TDC	Time-to-Digital Converter	Digital phase detector of an ADPLL.
XTAL	Crystal (reference oscillator)	40/50 MHz reference for PLL, ADC and digital.
DDS	Direct Digital Synthesizer	Digitally generated tone (IF test tone).
Kvco	VCO gain	Tuning sensitivity in MHz/V; varies per band.
AFC	Automatic Frequency Calibration (band calibration)	Picks the VCO capacitor-bank band before the PLL closes.
MMD	Multi-Modulus Divider	Programmable divider in the PLL feedback, dithered by the ΣΔ modulator.
CML	Current-Mode Logic	Fast differential logic used for the first divider (prescaler) stages at 20 GHz.

Data conversion & digital

Abbr.	Stands for	Note
SNM	Static Noise Margin	Noise an SRAM cell tolerates before flipping; read SNM is the critical one.
SEU	Single-Event Upset	Bit flip caused by a particle strike (soft error).
SER	Soft-Error Rate	Rate of radiation-induced bit flips, in FIT per Mbit.
MBU	Multi-Bit Upset	One particle flips several neighbouring cells.
RDF	Random Dopant Fluctuation	Random number of dopant atoms in a small channel; main cause of Vth mismatch.
LER	Line-Edge Roughness	Rough gate edges that add Vth variation in small devices.
NPSF	Neighbourhood Pattern-Sensitive Fault	Memory cell fails only for certain data in its neighbours.
SEC-DED	Single-Error Correction, Double-Error Detection	ECC code used on memory words (e.g. 64 + 8 bits).
ROM	Read-Only Memory	Mask-programmed memory for boot code and tables.
DRF	Data-Retention Fault	Memory cell loses its value after a pause.
WL	Word Line	Row select line of a memory array.
BL	Bit Line	Column data line of a memory array (BL and its complement BLB).
OSR	Oversampling Ratio	fs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR.
NTF	Noise Transfer Function	How a ΣΔ loop shapes quantisation noise out of the signal band.
SNDR	Signal-to-Noise-and-Distortion Ratio	ENOB = (SNDR − 1.76) / 6.02.
GBW	Gain-Bandwidth product	Op-amp figure of merit; sets filter and PGA accuracy at IF.
CMRR	Common-Mode Rejection Ratio	How well a differential circuit rejects signals common to both inputs.
CSI-2	MIPI Camera Serial Interface 2	High-speed serial link used for raw radar data.
TSN	Time-Sensitive Networking	Deterministic automotive Ethernet (IEEE 802.1).
ADC	Analog-to-Digital Converter	Main Rx ADCs (ΣΔ) and the aux SAR ADC.
DAC	Digital-to-Analog Converter	Rotator I/Q weights, bias, trim, test-tone generation.
SAR	Successive-Approximation Register ADC	Slow, precise ADC used for monitoring.
CT	Continuous-Time (CT-ΣΔ)	Sigma-delta ADC with a continuous-time loop filter.
ENOB	Effective Number of Bits
SFDR	Spurious-Free Dynamic Range	Tone relative to the largest spur.
THD	Total Harmonic Distortion
DR	Dynamic Range
INL	Integral Nonlinearity	Deviation from the ideal transfer line.
DNL	Differential Nonlinearity	Deviation of each step from 1 LSB.
LSB	Least Significant Bit (MSB = most significant)
DFE	Digital Front End	Decimation, DC and I/Q correction, interference handling.
CIC	Cascaded Integrator-Comb	Multiplier-free decimation filter.
FIR	Finite Impulse Response filter
DSP	Digital Signal Processor
MCU	Microcontroller Unit
CPU	Central Processing Unit	E.g. the RF control CPU that runs chirps and monitors.
SoC	System-on-Chip
ECU	Electronic Control Unit	Vehicle computer that receives radar data.
SRAM	Static RAM (RAM = random-access memory)
ECC	Error-Correcting Code	Memory protection for functional safety.
DMA	Direct Memory Access
LUT	Look-Up Table	E.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature.
FW	Firmware (SW = software)
OTP	One-Time Programmable memory	Holds trims and IDs, like eFuse.
SPI	Serial Peripheral Interface	Configuration / test bus from host or ATE.
CAN	Controller Area Network (CAN-FD = Flexible Data-rate)	Vehicle bus for object lists.
ETH	Ethernet (100/1000BASE-T1)	Automotive single-pair Ethernet.
CSI	Camera Serial Interface (MIPI CSI-2)	Streams raw radar data to a central SoC.
LVDS	Low-Voltage Differential Signaling	Raw-data debug / streaming interface.
GPIO	General-Purpose Input/Output
IO	Input/Output

Power

Abbr.	Stands for	Note
LDO	Low-Dropout regulator	Linear regulator; one per noise-sensitive domain.
PMIC	Power-Management IC	External bucks, supervisors and watchdog.
PSRR	Power-Supply Rejection Ratio	How much supply ripple an LDO (or circuit) blocks.
UV	Under-Voltage (OV = Over-Voltage)	Supply monitors, a safety mechanism.
OV	Over-Voltage	Rail above its window; OV monitor protects gate oxides.
POR	Power-On Reset	Holds the chip in reset until all rails are valid.
BOR	Brown-Out Reset	Resets when a supply sags during operation.
ESR	Equivalent Series Resistance	Of the LDO output capacitor; its zero affects loop stability.
OCP	Over-Current Protection	Current limit on a regulator output.
Iq	Quiescent current	Current a regulator draws for itself with no load.
DLDO	Digital LDO	Switched pass-device array regulated by a comparator loop.
GND	Ground

Test & production

Abbr.	Stands for	Note
EVB	Evaluation Board	Board that carries the chip on the bench with supplies, clock, interfaces and RF transitions.
SMU	Source-Measure Unit	Precision instrument that forces voltage or current and measures the other.
OTA	Over The Air	Measurement through antennas in a chamber instead of a cable or waveguide.
GSG	Ground-Signal-Ground probe	RF wafer probe with a signal tip between two ground tips.
LRRM	Line-Reflect-Reflect-Match calibration	On-wafer VNA calibration method for mmWave probes.
SCPI	Standard Commands for Programmable Instruments	Text command set used to automate instruments.
UPH	Units Per Hour	Test throughput of a tester and handler.
eFuse	Electrically programmable fuse	Silicided poly link blown by current; stores trim, ID and repair bits.
MTP	Multiple-Time Programmable memory	Small NVM that can be rewritten a few times.
NVM	Non-Volatile Memory	Keeps data without power: eFuse, OTP, MTP, flash.
VPP	Programming supply voltage	Supply used only to program fuses or OTP.
CRC	Cyclic Redundancy Check	Checksum that detects corrupted data, e.g. trim words at boot.
RMA	Return Material Authorization	A customer return, analysed through the 8D process.
8D	Eight Disciplines	Structured problem solving: team, describe, contain, root cause, correct, verify, prevent, close.
MSA	Measurement System Analysis	Proves a measurement is precise and accurate enough (Gage R&R, bias, stability).
GRR	Gage Repeatability and Reproducibility	%GRR < 10 % of tolerance is good.
BIST	Built-In Self-Test	On-chip stimulus + measurement; result is pass/fail or a value checked against a limit.
BISM	Built-In Self-Measurement	Same on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend.
DFT	Design for Test
ATE	Automatic Test Equipment	Production tester.
ATPG	Automatic Test Pattern Generation	Scan patterns for digital logic.
IDDQ	Quiescent supply-current test	Detects leakage defects.
PMU	Parametric Measurement Unit	ATE DC source/measure channel.
Cres	Contact resistance	Probe or socket contact resistance; measured with the Kelvin or two-current method.
FIMV	Force Current, Measure Voltage	PMU mode used for open/short (diode) tests.
FVMI	Force Voltage, Measure Current	PMU mode used for leakage and power-short tests.
IIL	Input leakage current, input Low (IIH = input High)	Leakage limit per IO pin, typically \|I\| < 1 µA.
IIH	Input leakage current, input High
ESD	Electrostatic Discharge	Pad protection diodes / clamps; the diode method uses them for continuity.
VDD	Positive supply rail (VSS = ground / negative rail)
VSS	Ground / negative supply rail
DCR	DC Resistance	E.g. of an RF shunt inductor, 0.5–3 Ω.
Hi-Z	High impedance (Z)	Output driver switched off; the pin floats.
OE	Output Enable	Control that switches an output between driving and Hi-Z.
IOZ	Off-state output leakage (IOZH at VDDIO, IOZL at 0 V)	Measured on a pin in Hi-Z; typically \|I\| < 1–10 µA.
VOH	Output High voltage threshold (VOL = Output Low)	Tester comparator levels that decide 1 / Z / 0.
VOL	Output Low voltage threshold
HIGHZ	IEEE 1149.1 instruction that puts all outputs in Hi-Z
EXTEST	IEEE 1149.1 external test instruction	Boundary cells drive and sample the pins; used for interconnect and walking-Z tests.
RPCT	Reduced Pin-Count Testing	Testing through JTAG / a few pins, so more sites fit on one tester.
BICS	Built-In Current Sensor	On-chip current monitor for IDDQ per power domain.
SPC	Statistical Process Control
VNA	Vector Network Analyzer	Lab instrument for S-parameters.
AWG	Arbitrary Waveform Generator
DMM	Digital Multimeter
GPIB	General-Purpose Interface Bus	Instrument control bus (like LAN).

Safety, standards & regulation

Abbr.	Stands for	Note
PMHF	Probabilistic Metric for random Hardware Failures	ISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D.
SEooC	Safety Element out of Context	A part developed to ISO 26262 against assumed system requirements.
FMEA	Failure Mode and Effects Analysis	Qualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage.
FIT	Failures In Time	Failures per 10⁹ device-hours.
MTTF	Mean Time To Failure
RED	Radio Equipment Directive (EU 2014/53/EU)	EU conformity framework for radio transmitters, including radar.
ASIL	Automotive Safety Integrity Level	ISO 26262 risk class A–D; radar typically ASIL-B.
ISO	ISO 26262 / ISO/SAE 21434 / ISO 11452	Functional safety / cybersecurity / EMC immunity.
FTTI	Fault-Tolerant Time Interval	Time from fault to hazard; monitors must react within it.
FMEDA	Failure Modes, Effects and Diagnostic Analysis
SPFM	Single-Point Fault Metric	ISO 26262 coverage metric.
LFM	Latent Fault Metric	ISO 26262 coverage metric.
AEC	Automotive Electronics Council (AEC-Q100 / Q200)	Qualification of ICs / passives.
ETSI	European Telecommunications Standards Institute	EN 301 091 / EN 303 396 radar standards.
FCC	Federal Communications Commission	US rules, Part 95M for 76–81 GHz.
EMC	Electromagnetic Compatibility
CISPR	Comité International Spécial des Perturbations Radioélectriques	CISPR 25: vehicle-component emissions.
OOB	Out-of-Band (emission)

Digital DFT, stress & reliability

Abbr.	Stands for	Note
UHST	Unbiased Highly Accelerated Stress Test	HAST without bias, 130 °C / 85 % RH; alternative to autoclave.
PTC	Power Temperature Cycling	Temperature cycling with the device powered on and off.
EDR	Endurance and Data Retention	Qualification of non-volatile memory (AEC-Q100-005).
DPA	Destructive Physical Analysis	Opening and sectioning parts to inspect their construction and damage.
SEM	Scanning Electron Microscope	High-magnification imaging of cross-sections and surfaces.
EDX	Energy-Dispersive X-ray spectroscopy	Element analysis in the SEM: corrosion, contamination, IMC phases.
FIB	Focused Ion Beam	Precise local cutting and imaging; also used for circuit edits.
LTPD	Lot Tolerance Percent Defective	Defect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %.
PC	Preconditioning	Bake, moisture soak and reflow before environmental stress (JESD22-A113).
BLR	Board-Level Reliability	Reliability of the package soldered on a PCB (temperature cycling, drop, vibration).
SAC	Tin-Silver-Copper solder	Lead-free solder alloy (e.g. SAC305) used for balls.
PPAP	Production Part Approval Process	Automotive approval package, includes the qualification report.
DRC	Design Rule Check	Verifies layout against foundry manufacturing rules.
LVS	Layout Versus Schematic	Verifies that the layout matches the schematic netlist.
PEX	Parasitic Extraction	Extracts resistance, capacitance (and inductance) of the layout for post-layout simulation.
AMS	Analog / Mixed-Signal simulation	Simulation that combines transistor-level analog with digital models.
ECO	Engineering Change Order	Late design fix; a metal-only ECO changes only upper masks.
SCR	Silicon-Controlled Rectifier	Thyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up.
GGNMOS	Grounded-Gate NMOS	ESD clamp that works by parasitic-bipolar snapback.
SE	Scan Enable	Selects shift (SE = 1) or functional capture (SE = 0) in scan flops.
SAF	Stuck-At Fault	Node permanently 0 or 1.
TDF	Transition Delay Fault	Node slow to rise or fall; needs at-speed test.
STA	Static Timing Analysis	Finds the longest paths for timing-aware ATPG.
OCV	On-Chip Variation	Timing derates in STA that account for local (mismatch) variation across the die.
OCC	On-Chip Clock Controller	Gates exact launch/capture pulses from the PLL for at-speed test.
LOC	Launch-On-Capture	At-speed scheme; also called broadside.
LOS	Launch-On-Shift	At-speed scheme; SE must switch at speed.
EDT	Embedded Deterministic Test	Scan compression (decompressor + compactor).
LFSR	Linear-Feedback Shift Register	Pseudo-random sequence generator.
PRPG	Pseudo-Random Pattern Generator	LFSR that feeds the scan chains in LBIST.
MISR	Multiple-Input Signature Register	Compresses responses into one signature.
STUMPS	Self-Test Using MISR and Parallel Shift-register sequence generator	Standard LBIST architecture.
LBIST	Logic BIST	On-chip random-pattern scan test; used at key-on.
MBIST	Memory BIST	On-chip March-algorithm test of SRAMs.
BIRA	Built-In Redundancy Analysis	Computes which spare rows/columns repair a memory.
BISR	Built-In Self-Repair	Loads the repair from eFuse at boot.
IR	IR drop	Supply voltage drop (current × resistance), high during scan shift.
JTAG	Joint Test Action Group (IEEE 1149.1)	Boundary scan and test access port.
TAP	Test Access Port	JTAG pins TCK, TMS, TDI, TDO, TRST.
BSDL	Boundary Scan Description Language	Describes a chip's JTAG boundary-scan cells.
IJTAG	Internal JTAG (IEEE 1687)	Network for accessing on-chip instruments.
MUX	Multiplexer	Selects one of N inputs; in test, routes sub-block nodes to shared instruments.
ATB	Analog Test Bus	Chip-wide wire pair (force + sense) that test muxes connect sub-block nodes to.
TG	Transmission Gate	Parallel NMOS + PMOS switch; passes the full voltage range.
SPDT	Single-Pole Double-Throw switch	One input to one of two outputs (SP4T = one of four).
BBM	Break-Before-Make	Switching order that opens the old path before closing the new one.
ICL	Instrument Connectivity Language (PDL = Procedural Description Language)	IJTAG description files.
ECID	Electronic Chip ID	Unique per-die ID for traceability.
HVST	High-Voltage Stress Test	Short over-voltage on the core rail to activate latent oxide defects.
VLV	Very-Low-Voltage test	Test below nominal V to expose resistive defects.
Vmin	Minimum operating voltage	The pass/fail edge in a shmoo; an outlier Vmin flags a defect.
PAT	Part Average Testing (AEC-Q001)	Outlier limits at robust μ ± 6σ.
DPAT	Dynamic Part Average Testing	PAT limits recalculated per lot or wafer.
GDBN	Good Die in Bad Neighbourhood	Wafer-map screen that rejects dies in defect clusters.
NNR	Nearest-Neighbour Residual	Compares a die's parameter with its wafer neighbours.
DPPM	Defective Parts Per Million	Shipped-quality metric; automotive target ≪ 1.
FT	Final Test	Package-level production test.
SLT	System-Level Test	Functional test by booting the application.
PCM	Process Control Monitor	Test structures in the scribe lines, measured by the fab (see WAT).
WAT	Wafer Acceptance Test	Fab's electrical test of PCM structures before shipping wafers.
OSAT	Outsourced Semiconductor Assembly and Test	Company that packages and tests the dies.
QA	Quality Assurance	Sample-based outgoing inspection and audits.
Cp	Process capability (Cp)	(USL − LSL) / 6σ: spec width vs process spread.
Cpk	Process capability index	min(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67.
USL	Upper Spec Limit (LSL = Lower Spec Limit)	Design limits; outside them the part is out of spec.
LSL	Lower Spec Limit
UCL	Upper Control Limit (LCL = Lower Control Limit)	Process limits from history, usually mean ± 3σ.
LCL	Lower Control Limit
OCAP	Out-of-Control Action Plan	Documented steps when an SPC rule fires.
MRB	Material Review Board	Decides what happens to held material: release, rework, scrap or deviation.
MIM	Metal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal)	Precision on-chip capacitors.
MOM	Metal-Oxide-Metal (finger) capacitor
BSIM	Berkeley Short-channel IGFET Model	Industry-standard compact transistor model family used in design kits.
Vt	Threshold voltage	Gate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD.
Idsat	Saturation drain current	Id at Vgs = Vds = VDD, per µm of width; transistor strength.
Ioff	Off-state leakage current	Id at Vgs = 0, Vds = VDD.
DIBL	Drain-Induced Barrier Lowering	Vt drop per volt of Vds in short-channel devices.
SS	Subthreshold swing (also SS = slow-slow process corner)	mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature.
TT	Typical-typical process corner	FF = fast-fast; FS / SF = skewed NMOS / PMOS corners.
FF	Fast-fast process corner
gm	Transconductance	∂Id/∂Vgs; the transistor's gain.
gds	Output conductance	∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds).
Cox	Gate-oxide capacitance per area	εox / Tox.
Tox	Gate-oxide thickness	Measured with C-V structures in WAT.
fT	Transit (unity current-gain) frequency	≈ gm / 2π(Cgs + Cgd).
fmax	Maximum oscillation (unity power-gain) frequency	Needs ≈ 3–4× the operating frequency for useful gain.
Vbd	Gate-oxide breakdown voltage	Voltage where oxide current jumps past compliance in a V-ramp test.
BV	Breakdown Voltage	BVdss = drain-source (gate off), BVj = junction.
BVdss	Drain-source breakdown voltage	Transistor off-state breakdown; limits PA drain swing.
BVj	Junction breakdown voltage	Reverse breakdown of N+/P-well or P+/N-well diodes.
TLP	Transmission-Line Pulse	ESD device characterisation with short, high-current pulses.
QBD	Charge to breakdown	Total charge an oxide passes before breaking down (reliability).
IMD	Inter-Metal Dielectric	Insulator between metal lines/layers; tested with comb structures.
CMP	Chemical-Mechanical Planarization	Polishing step that flattens each layer; source of centre, edge and ring signatures.
OPC	Optical Proximity Correction	Mask shape corrections; weak spots (hotspots) can fail per reticle shot.
EBR	Edge Bead Removal	Removes resist build-up at the wafer edge.
D0	Defect density	Random defects per unit area; baseline yield Y ≈ e^(−D0·A).
HTOL	High-Temperature Operating Life	≈ 1000 h biased at max temperature (AEC-Q100).
ELFR	Early Life Failure Rate	Short high-temperature operation of a large sample.
TC	Temperature Cycling	Package and interconnect fatigue test.
THB	Temperature-Humidity-Bias	85 °C / 85% RH with bias.
HAST	Highly Accelerated Stress Test	130 °C / 85% RH with bias.
RH	Relative Humidity
HTSL	High-Temperature Storage Life	Unbiased bake.
HBM	Human-Body Model (ESD)
CDM	Charged-Device Model (ESD)
LU	Latch-Up	JESD78 test.
EM	Electromigration	Metal wear-out under current (wafer-level reliability).
TDDB	Time-Dependent Dielectric Breakdown	Gate-oxide wear-out.
HCI	Hot-Carrier Injection	Transistor degradation mechanism.
NBTI	Negative-Bias Temperature Instability	PMOS threshold drift.

PCB, package & materials

Abbr.	Stands for	Note
TCB	Thermo-Compression Bonding	Flip-chip attach with heat and force per die; fine pitch, low warpage.
MUF	Molded Underfill	Mold compound that also fills the gap under a flip-chip die.
CSAM	C-mode Scanning Acoustic Microscopy	Ultrasound imaging of voids and delamination inside packages.
AOI	Automated Optical Inspection	Camera inspection of RDL, bumps and balls in the assembly line.
KGD	Known-Good Die	Die that passed wafer sort and is released for assembly.
WLP	Wafer-Level Package	Package built on the whole wafer (fan-in) or a reconstituted wafer (fan-out).
PCB	Printed Circuit Board
RDL	Redistribution Layer	Thin-film Cu wiring that routes die pads to balls (fan-out) or bumps.
UBM	Under-Bump Metallisation	Metal stack between die/RDL pad and the solder.
FOWLP	Fan-Out Wafer-Level Package	Die embedded in mold with RDL fanning out to balls; eWLB is one type.
CSP	Chip-Scale Package	Package only slightly larger than the die (FC-CSP = flip-chip CSP).
AiP	Antenna-in-Package	Antennas built into package layers.
IMC	Intermetallic Compound	Layer formed between solder and UBM/pad; grows with time and temperature.
CTE	Coefficient of Thermal Expansion	Mismatch between materials drives solder and bump fatigue.
MSL	Moisture Sensitivity Level	J-STD-020 rating: how long a package may sit out of dry pack before reflow.
ELK	Extreme Low-k dielectric	Fragile back-end dielectric in advanced nodes; cracks under bump stress.
NSMD	Non-Solder-Mask-Defined pad	PCB pad style that improves solder-joint fatigue life.
Dk	Dielectric constant	Sets line impedance and antenna tuning; shifts with moisture.
Df	Dissipation factor	Dielectric loss; key for RF loss at 77 GHz.
C-SAM	C-mode Scanning Acoustic Microscopy	Non-destructive imaging of delamination and voids.
PBO	Polybenzoxazole	Polymer dielectric used in RDL (like polyimide).
EOS	Electrical Overstress	Damage from overvoltage or overcurrent beyond ESD events.
BGA	Ball Grid Array	FC-BGA = flip-chip BGA.
eWLB	embedded Wafer-Level Ball-grid-array	Fan-out package with low RF loss.
AoP	Antenna-on-Package
LoP	Launch-on-Package	RF launched from package into waveguide / antenna.
GCPW	Grounded Coplanar Waveguide	PCB transmission line at the ball launch.
SIW	Substrate-Integrated Waveguide	Waveguide formed with via fences in the PCB.
FR4	Flame-Retardant epoxy-glass laminate	Standard low-cost PCB material.
ENEPIG	Electroless Nickel, Electroless Palladium, Immersion Gold	PCB surface finish.
ImAg	Immersion Silver	PCB surface finish.
HASL	Hot-Air Solder Leveling	Surface finish; too rough/uneven for 77 GHz.
PBT	Polybutylene terephthalate (PC = polycarbonate)	Radome plastics.
HFSS	High-Frequency Structure Simulator (Ansys)	3D EM simulator (CST = Dassault's equivalent).