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77 GHz radar SoC · memory

Embedded SRAM: design, test and process faults

How the on-chip SRAM of a radar SoC is designed (6T cell, margins, assists, ECC, redundancy), how it is tested (fault models, March algorithms, Vmin and shmoo, retention), how process problems show up as faults and bitmaps, and how repair and field monitoring work. Includes a memory-size-to-cell-sigma calculator.

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Embedded SRAM: design, test and process faults

MemoryTest

A radar SoC carries several megabytes of on-chip SRAM: the radar-cube memory, DSP and CPU memories, buffers in the data path, plus ROM and register files. Memories are the densest structures on the die, so they collect a large share of the random defects, and their smallest transistors are the most sensitive to process variation. This page covers how an embedded SRAM is built, how it is tested and repaired, and how each process problem shows up as a memory fault. The test infrastructure (MBIST controller, March algorithms in the scan context) is introduced on the DFT page.

The 6T bitcell

WL (word line)BLBLBPG-L (access)PG-R (access)QQBINV1: PU1 (PMOS) + PD1 (NMOS)INV2: PU2 + PD2Read: precharge BL/BLB high, raise WL; the side storing 0 pulls its bit line down; the sense amp detects ≈ 50–150 mV.
The six-transistor SRAM cell. Its three device pairs fight each other on purpose: during a read the pull-down must beat the access transistor (read stability), during a write the access transistor must beat the pull-up (writability).
Cell ratio (read stability) β = (W/L)_PD / (W/L)_PG ≈ 1.5–2 Pull-up ratio (writability) γ = (W/L)_PU / (W/L)_PG < 1 Mismatch (Pelgrom) σ(ΔVth) = A_VT / √(W·L) → largest in the smallest (bitcell) devices Read signal on the bit line ΔV_BL = I_read · t / C_BL ≈ 50–150 mV when the sense amp fires

Design metrics and techniques

MetricWhat it meansTypical targetSet by
Read static noise margin (SNM)How much noise the cell tolerates while being read without flipping≥ 100–150 mV at Vmin, worst cornerCell ratio β = PD/PG strength ≈ 1.5–2
Write marginHow easily a write flips the cellPositive at Vmin, slow PMOS-fast NMOS cornerPull-up ratio PU/PG < 1, write assist
Read current I_readBit-line discharge speedEnough for access time at the slow cornerPG and PD sizing, Vth
VminLowest supply where every bit worksBelow the minimum operating supply with marginMismatch (σVth) of the smallest devices
Leakage / retentionStandby current, data retention at low supplyµA per Mb at hot; retention voltage ≈ 0.5–0.6 VVth flavour, temperature
Access / cycle timeRead latency, clock rateMatches the DSP or CPU clockSelf-timed sense-amp enable, bit-line length
  • Assist circuits widen the margins at low voltage: word-line under-drive (read), negative bit line or cell-supply collapse (write).
  • Dual rail: the array runs on its own supply (often slightly higher) while the periphery follows the logic supply.
  • Self-timed read: a replica bit line fires the sense amplifier when enough signal has built up, tracking process and temperature.
  • ECC: SEC-DED code words (e.g. 64 data + 8 check bits) correct single-bit errors and detect double; required for safety-relevant radar-cube memory (safety mechanisms).
Row decoderWL driversbitcell array (e.g. 512 rows × 256 columns per sub-array)spare rowsspare columnsPrecharge / equaliseColumn mux · sense amps · write driversTiming & controlself-timedMBIST + BIRAMarch tests, repairFuse boxrepair addresses→ eFuse / OTP page
Inside a memory macro. Spare rows and columns are wired in so that failing ones can be replaced; the repair information is stored in fuses and loaded at power-up.

Why memories need 6σ cells

Every one of millions of cells must work, so the worst cell sets the yield. With mismatch spread σ(ΔVth), a memory of N bits needs each cell to survive roughly 5–6σ of variation at Vmin. Redundancy relaxes this: if a few failing bits can be repaired, the per-cell requirement drops noticeably.

Memory size → required cell sigma

Poisson model: yield = P(failing bits ≤ repairable). The cell margin is the number of σ of Vth mismatch the worst cell must survive at Vmin.

Number of bitcells–
Allowed mean failing bits per array–
Allowed fail probability per cell–
–
Required cell margin–

Fault models

Fault modelWhat happens
Stuck-at (SAF)Cell always reads 0 or 1
Transition (TF)Cell cannot change 0→1 or 1→0
Coupling (CF: inversion, idempotent, state)Writing or holding one cell changes another
Address-decoder (AF)An address selects no cell, several cells, or the wrong cell
Data retention (DRF)Cell loses its value after a pause, often only at hot
Read / write disturbA read or write flips the cell itself or a neighbour
Stuck-open (SOF)Open access path: the read returns the previous value
Neighbourhood pattern (NPSF)A cell fails only for a specific pattern in its physical neighbours

March algorithms

AlgorithmNotation (⇑ up, ⇓ down, ⇕ either)LengthDetects
MATS+⇕(w0); ⇑(r0,w1); ⇓(r1,w0)5NStuck-at, address-decoder faults
March C−⇕(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇕(r0)10NStuck-at, transition, address, unlinked coupling faults
March SS6 elements with read-after-read and write-after-read operations22NStatic simple faults incl. read- and write-disturb, deceptive read
Checkerboard + pauseWrite checkerboard, wait (e.g. 100 ms at hot), read4N + pauseData-retention faults, leakage, weak pull-up
Address-scrambled / neighbourhoodPhysical-layout-aware patternsvariesBridges between physical neighbours, NPSF
March C− (10N): ⇕(w0) ⇑(r0,w1) ⇑(r1,w0) ⇓(r0,w1) ⇓(r1,w0) ⇕(r0) test time ≈ 10 · N · t_cycle e.g. 8 Mbit organised as 128 k × 64 at 400 MHz → 10 · 131 072 · 2.5 ns ≈ 3.3 ms

Process causes and how they show up

Process causePhysical defectFault modelTypical bitmapTest that catches it
Particle (any layer)Extra or missing material across cellsStuck-at, couplingClusterMarch C−; GDBN on the wafer map
CMP / litho (metal)Bridge between bit lines or word linesCoupling / bridging, address faultDouble bit, double row/columnMarch with physical scrambling
Contact / via etchResistive or open contact to a cell node or bit lineTransition fault, slow read, stuck-openSingle bit, columnAt-speed March, Vmin and hot tests
Random dopant fluctuation, line-edge roughnessLarge Vth mismatch in one cellRead-disturb, write fail at low voltageSingle bits that appear only at VminVmin test, March SS, shmoo
Gate-oxide defectOxide short or weak oxideStuck-at, leakageSingle bit, IDDQ riseIDDQ, March, HTOL
Junction leakage, weak PMOS (aging NBTI)Node loses chargeData-retention faultSingle bits at hotRetention pause test at hot
Decoder / word-line defectWL open or short, decoder gate faultAddress-decoder faultFull row or address aliasingMarch (MATS+ minimum)
Sense amp / column circuit mismatchOffset larger than the bit-line signalColumn read failFull columnMarch at slow corner, Vmin
Alpha particles / neutrons (not a defect)Charge from radiation flips a cellSoft error (SEU, MBU)Random single bits in the fieldECC, scrubbing; SER test with a beam

A fail bitmap turns MBIST results into a picture of the array; the shape points to the cause. Bitmaps from many dies are overlaid like wafer maps (wafer-map signatures) and correlated with PCM data (PCM / WAT).

single bitdouble bitrow (WL) failcolumn (BL) failcluster
Illustrative bitmap of one sub-array. Single bits: weak cell or random defect; double bits: bridge between neighbours; a row: word-line or decoder defect; a column: bit-line short or sense-amp offset; a cluster: particle.
SignatureMost likely causeNext step
Single bit, only at Vmin or slow cornerMismatch (RDF), weak cellShmoo, compare with Vth-mismatch PCM structures
Single bit, only at hot after a pauseJunction leakage, weak pull-upRetention test at several pause times
Double bit (adjacent)Metal or contact bridgePhysical FA at that location
Row or row pairWord-line short or open, decoderCheck WL resistance, decoder logic
ColumnBit-line short, sense-amp offset, column muxColumn-circuit test, Vmin
ClusterParticle, local process excursionInline defect inspection images at that x/y
Whole bankPower, clock or I/O of the macroSupply and timing checks

Vmin and shmoo testing

200 MHz, 0.70 V: fail200 MHz, 0.72 V: fail200 MHz, 0.74 V: pass200 MHz, 0.76 V: pass200 MHz, 0.78 V: pass200 MHz, 0.80 V: pass200 MHz, 0.82 V: pass200 MHz, 0.84 V: pass200 MHz, 0.86 V: pass200 MHz, 0.88 V: pass200 MHz, 0.90 V: pass200 MHz, 0.92 V: pass200 MHz, 0.94 V: pass200 MHz, 0.96 V: pass200 MHz, 0.98 V: pass200 MHz, 1.00 V: pass240 MHz, 0.70 V: fail240 MHz, 0.72 V: fail240 MHz, 0.74 V: fail240 MHz, 0.76 V: pass240 MHz, 0.78 V: pass240 MHz, 0.80 V: pass240 MHz, 0.82 V: pass240 MHz, 0.84 V: pass240 MHz, 0.86 V: pass240 MHz, 0.88 V: pass240 MHz, 0.90 V: pass240 MHz, 0.92 V: pass240 MHz, 0.94 V: pass240 MHz, 0.96 V: pass240 MHz, 0.98 V: pass240 MHz, 1.00 V: pass280 MHz, 0.70 V: fail280 MHz, 0.72 V: fail280 MHz, 0.74 V: fail280 MHz, 0.76 V: pass280 MHz, 0.78 V: pass280 MHz, 0.80 V: pass280 MHz, 0.82 V: pass280 MHz, 0.84 V: pass280 MHz, 0.86 V: pass280 MHz, 0.88 V: pass280 MHz, 0.90 V: pass280 MHz, 0.92 V: pass280 MHz, 0.94 V: pass280 MHz, 0.96 V: pass280 MHz, 0.98 V: pass280 MHz, 1.00 V: pass320 MHz, 0.70 V: fail320 MHz, 0.72 V: fail320 MHz, 0.74 V: fail320 MHz, 0.76 V: fail320 MHz, 0.78 V: pass320 MHz, 0.80 V: pass320 MHz, 0.82 V: pass320 MHz, 0.84 V: pass320 MHz, 0.86 V: pass320 MHz, 0.88 V: pass320 MHz, 0.90 V: pass320 MHz, 0.92 V: pass320 MHz, 0.94 V: pass320 MHz, 0.96 V: pass320 MHz, 0.98 V: pass320 MHz, 1.00 V: pass360 MHz, 0.70 V: fail360 MHz, 0.72 V: fail360 MHz, 0.74 V: fail360 MHz, 0.76 V: fail360 MHz, 0.78 V: fail360 MHz, 0.80 V: pass360 MHz, 0.82 V: pass360 MHz, 0.84 V: pass360 MHz, 0.86 V: pass360 MHz, 0.88 V: pass360 MHz, 0.90 V: pass360 MHz, 0.92 V: pass360 MHz, 0.94 V: pass360 MHz, 0.96 V: pass360 MHz, 0.98 V: pass360 MHz, 1.00 V: pass400 MHz, 0.70 V: fail400 MHz, 0.72 V: fail400 MHz, 0.74 V: fail400 MHz, 0.76 V: fail400 MHz, 0.78 V: fail400 MHz, 0.80 V: pass400 MHz, 0.82 V: pass400 MHz, 0.84 V: pass400 MHz, 0.86 V: pass400 MHz, 0.88 V: pass400 MHz, 0.90 V: pass400 MHz, 0.92 V: pass400 MHz, 0.94 V: pass400 MHz, 0.96 V: pass400 MHz, 0.98 V: pass400 MHz, 1.00 V: pass440 MHz, 0.70 V: fail440 MHz, 0.72 V: fail440 MHz, 0.74 V: fail440 MHz, 0.76 V: fail440 MHz, 0.78 V: fail440 MHz, 0.80 V: fail440 MHz, 0.82 V: pass440 MHz, 0.84 V: pass440 MHz, 0.86 V: pass440 MHz, 0.88 V: pass440 MHz, 0.90 V: pass440 MHz, 0.92 V: pass440 MHz, 0.94 V: pass440 MHz, 0.96 V: pass440 MHz, 0.98 V: pass440 MHz, 1.00 V: pass480 MHz, 0.70 V: fail480 MHz, 0.72 V: fail480 MHz, 0.74 V: fail480 MHz, 0.76 V: fail480 MHz, 0.78 V: fail480 MHz, 0.80 V: fail480 MHz, 0.82 V: fail480 MHz, 0.84 V: pass480 MHz, 0.86 V: pass480 MHz, 0.88 V: pass480 MHz, 0.90 V: pass480 MHz, 0.92 V: pass480 MHz, 0.94 V: pass480 MHz, 0.96 V: pass480 MHz, 0.98 V: pass480 MHz, 1.00 V: pass520 MHz, 0.70 V: fail520 MHz, 0.72 V: fail520 MHz, 0.74 V: fail520 MHz, 0.76 V: fail520 MHz, 0.78 V: fail520 MHz, 0.80 V: fail520 MHz, 0.82 V: fail520 MHz, 0.84 V: fail520 MHz, 0.86 V: pass520 MHz, 0.88 V: pass520 MHz, 0.90 V: pass520 MHz, 0.92 V: pass520 MHz, 0.94 V: pass520 MHz, 0.96 V: pass520 MHz, 0.98 V: pass520 MHz, 1.00 V: pass560 MHz, 0.70 V: fail560 MHz, 0.72 V: fail560 MHz, 0.74 V: fail560 MHz, 0.76 V: fail560 MHz, 0.78 V: fail560 MHz, 0.80 V: fail560 MHz, 0.82 V: fail560 MHz, 0.84 V: fail560 MHz, 0.86 V: fail560 MHz, 0.88 V: pass560 MHz, 0.90 V: pass560 MHz, 0.92 V: pass560 MHz, 0.94 V: pass560 MHz, 0.96 V: pass560 MHz, 0.98 V: pass560 MHz, 1.00 V: pass600 MHz, 0.70 V: fail600 MHz, 0.72 V: fail600 MHz, 0.74 V: fail600 MHz, 0.76 V: fail600 MHz, 0.78 V: fail600 MHz, 0.80 V: fail600 MHz, 0.82 V: fail600 MHz, 0.84 V: fail600 MHz, 0.86 V: fail600 MHz, 0.88 V: fail600 MHz, 0.90 V: pass600 MHz, 0.92 V: pass600 MHz, 0.94 V: pass600 MHz, 0.96 V: pass600 MHz, 0.98 V: pass600 MHz, 1.00 V: pass640 MHz, 0.70 V: fail640 MHz, 0.72 V: fail640 MHz, 0.74 V: fail640 MHz, 0.76 V: fail640 MHz, 0.78 V: fail640 MHz, 0.80 V: fail640 MHz, 0.82 V: fail640 MHz, 0.84 V: fail640 MHz, 0.86 V: fail640 MHz, 0.88 V: fail640 MHz, 0.90 V: fail640 MHz, 0.92 V: pass640 MHz, 0.94 V: pass640 MHz, 0.96 V: pass640 MHz, 0.98 V: pass640 MHz, 1.00 V: pass680 MHz, 0.70 V: fail680 MHz, 0.72 V: fail680 MHz, 0.74 V: fail680 MHz, 0.76 V: fail680 MHz, 0.78 V: fail680 MHz, 0.80 V: fail680 MHz, 0.82 V: fail680 MHz, 0.84 V: fail680 MHz, 0.86 V: fail680 MHz, 0.88 V: fail680 MHz, 0.90 V: fail680 MHz, 0.92 V: fail680 MHz, 0.94 V: pass680 MHz, 0.96 V: pass680 MHz, 0.98 V: pass680 MHz, 1.00 V: pass720 MHz, 0.70 V: fail720 MHz, 0.72 V: fail720 MHz, 0.74 V: fail720 MHz, 0.76 V: fail720 MHz, 0.78 V: fail720 MHz, 0.80 V: fail720 MHz, 0.82 V: fail720 MHz, 0.84 V: fail720 MHz, 0.86 V: fail720 MHz, 0.88 V: fail720 MHz, 0.90 V: fail720 MHz, 0.92 V: fail720 MHz, 0.94 V: fail720 MHz, 0.96 V: pass720 MHz, 0.98 V: pass720 MHz, 1.00 V: pass760 MHz, 0.70 V: fail760 MHz, 0.72 V: fail760 MHz, 0.74 V: fail760 MHz, 0.76 V: fail760 MHz, 0.78 V: fail760 MHz, 0.80 V: fail760 MHz, 0.82 V: fail760 MHz, 0.84 V: fail760 MHz, 0.86 V: fail760 MHz, 0.88 V: fail760 MHz, 0.90 V: fail760 MHz, 0.92 V: fail760 MHz, 0.94 V: fail760 MHz, 0.96 V: fail760 MHz, 0.98 V: pass760 MHz, 1.00 V: pass800 MHz, 0.70 V: fail800 MHz, 0.72 V: fail800 MHz, 0.74 V: fail800 MHz, 0.76 V: fail800 MHz, 0.78 V: fail800 MHz, 0.80 V: fail800 MHz, 0.82 V: fail800 MHz, 0.84 V: fail800 MHz, 0.86 V: fail800 MHz, 0.88 V: fail800 MHz, 0.90 V: fail800 MHz, 0.92 V: fail800 MHz, 0.94 V: fail800 MHz, 0.96 V: fail800 MHz, 0.98 V: fail800 MHz, 1.00 V: pass2002803604405206006807600.700.760.820.880.941.00spec point 600 MHz, 0.92 V (≈ 40 mV above Vmin)clock frequency (MHz)memory supply (V)
Illustrative shmoo: memory passes above a Vmin boundary that rises with clock frequency. Production tests at a guard-banded Vmin; the margin between the boundary and the spec point shrinks with aging (NBTI) and at the slow corner. Hover cells for values.
  • VLV / Vmin test catches weak cells and resistive defects that pass at nominal supply (VLV).
  • Aging guard band: NBTI raises Vmin over life; HTOL data sets the margin (reliability).
  • Temperature: retention and leakage at hot, read margin often worst at cold for some processes; both corners are tested.

Test, repair and field operation

StepWhat happensLink
Wafer sortMBIST at Vmin, nominal and Vmax, hot; built-in repair analysis (BIRA) allocates spare rows/columnsMBIST
RepairRepair addresses burned into eFuse; retest to confirm the repaireFuse / OTP
Final testMBIST again (after packaging stress), retention, Vmintest flow
DiagnosisBitmaps of failing dies → yield learning and physical FAyield
Key-on (in the car)MBIST on safety-relevant memories at every start; repair loaded from fuseskey-on tests
OperationECC corrects single-bit errors; background scrubbing; error counters reportedsafety mechanisms

Soft errors

  • Alpha particles (from package materials and solder) and atmospheric neutrons deposit charge and flip cells. They are not defects: the cell is fine afterwards.
  • Soft-error rate is quoted in FIT per Mbit; at advanced nodes multi-bit upsets (MBU) in neighbouring cells become common, so ECC words are interleaved so that physical neighbours belong to different words.
  • Low-alpha mold and solder materials, ECC with scrubbing, and parity on registers keep the radar within its safety budget (PMHF).

Process monitors for memory

PCM / WAT itemLinks to
Bitcell Vth and Idsat (PD, PG, PU) and their mismatch arraysRead SNM, write margin, Vmin
SRAM test arrays (SNM, read current, leakage)Early warning of a memory yield shift
Contact and via chain resistanceResistive opens, slow read
Junction and gate leakage at hotRetention, standby current
Defect density (D0) from inline inspectionCluster and bridge fails (yield model)
Values are typical for 77 GHz automotive radar SoCs and meant for planning; check your process, product and customer requirements.
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Glossary of abbreviations

Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.

Radar system & ADAS

Abbr.Stands forNote
FCWForward Collision WarningWarns of an imminent frontal collision; stage before AEB.
FCTAFront Cross-Traffic AlertFront corner-radar function at junctions and driveways.
RCTBRear Cross-Traffic BrakingBrakes automatically when RCTA detects cross traffic while reversing.
DOWDoor-Opening WarningWarns before a door is opened into an approaching cyclist or car.
VRUVulnerable Road UserPedestrians, cyclists and motorcyclists.
TTCTime To CollisionRange divided by closing speed; triggers warnings and braking.
LRRLong-Range RadarFront radar, ≈ 200–300 m, narrow field of view.
MRRMid-Range Radar≈ 80–160 m, ±40–60° field of view.
SRRShort-Range RadarCorner radar, ≈ 30–80 m, ±75–90° field of view.
NCAPNew Car Assessment ProgrammeConsumer safety ratings (Euro NCAP, C-NCAP, IIHS …).
GSRGeneral Safety Regulation (EU) 2019/2144Makes AEB and other assistance functions mandatory in the EU.
CPDChild Presence DetectionIn-cabin sensing (often 60 GHz radar) that detects a child left in the car.
ACCAdaptive Cruise ControlKeeps distance to the car ahead; uses long-range front radar.
ADASAdvanced Driver-Assistance SystemsThe vehicle functions the radar serves.
AEBAutonomous Emergency BrakingBrakes automatically when a collision is imminent.
BSDBlind-Spot DetectionCorner-radar function.
LCALane-Change AssistCorner-radar function that warns of fast approaching vehicles.
RCTARear Cross-Traffic AlertRear corner-radar function when reversing.
L2SAE automation Level 2 (L3 = Level 3)Partial (L2) and conditional (L3) driving automation.
FMCWFrequency-Modulated Continuous WaveA linear chirp; range comes from the beat frequency f_b = S·2R/c.
FoVField of ViewAngular coverage in azimuth and elevation.
RCSRadar Cross SectionTarget reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0).
dBsmDecibels relative to 1 m²Unit of RCS.
EIRPEffective Isotropic Radiated PowerTx power + antenna gain; limited by regulations.
MIMOMultiple-Input Multiple-OutputN_tx × N_rx channels form a larger virtual array.
TDMTime-Division MultiplexingOne Tx per chirp; v_max falls by a factor of N_tx.
BPMBinary Phase Modulation0/180° codes across chirps separate the Tx signals.
DDMADoppler-Division Multiple AccessEach Tx gets a slow-time phase ramp and separates in Doppler.
DoADirection of ArrivalAngle estimation over the virtual array.
DBFDigital BeamformingFFT or matched steering over array channels.
CFARConstant False Alarm RateAdaptive detection threshold (CA = cell-averaging, OS = ordered-statistic).
FFTFast Fourier TransformRange, Doppler and angle FFTs build the radar cube.
SNRSignal-to-Noise Ratio
MUSICMUltiple SIgnal ClassificationSubspace super-resolution DoA algorithm.
ESPRITEstimation of Signal Parameters via Rotational Invariance TechniquesSuper-resolution DoA algorithm.
IAAIterative Adaptive ApproachSuper-resolution spectral / DoA estimator.
DBSCANDensity-Based Spatial Clustering of Applications with NoiseGroups detections into objects.
EKFExtended Kalman FilterNonlinear tracking filter.
UKFUnscented Kalman FilterNonlinear tracking filter using sigma points.
IMMInteracting Multiple ModelTracker that mixes several motion models.
HWAHardware AcceleratorOn-chip FFT / radar processing engine.
RTSRadar Target SimulatorEcho generator for HIL and EOL testing.
HILHardware-in-the-LoopTesting the real sensor against simulated scenarios.
EOLEnd-of-LineFinal production test of a module or vehicle.

RF & analog front end

Abbr.Stands forNote
HPBWHalf-Power BeamwidthAngle between the −3 dB points of an antenna or array beam.
PDNPower Delivery NetworkRegulators, planes, decoupling and package paths that supply the chip.
PIPower IntegrityKeeping supply voltage within limits under load steps and noise.
EMIElectromagnetic InterferenceUnwanted emission or pick-up of electromagnetic energy.
BCIBulk Current InjectionImmunity test (ISO 11452-4) that injects RF current into a cable harness.
TIMThermal Interface MaterialGap pad or paste between board or package and the heat sink.
RFRadio FrequencyHere the 76–81 GHz signal.
LOLocal OscillatorThe chirp signal that drives the Tx and the Rx mixers.
IFIntermediate FrequencyThe beat / baseband signal after the mixer, DC–20 MHz.
PAPower AmplifierTx output stage, 12–14 dBm.
LNALow-Noise AmplifierFirst Rx stage; sets most of the NF.
NFNoise FigureNoise the receiver adds, in dB.
VGAVariable-Gain AmplifierProgrammable-gain stage (IF), or signed VGAs in the phase rotator.
TIATransimpedance AmplifierCurrent-to-voltage stage after a passive mixer.
HPFHigh-Pass FilterIn IF: removes leakage and DC, and equalises R⁻⁴.
LPFLow-Pass Filter
AAFAnti-Aliasing FilterLow-pass filter in front of the ADC.
PPFPolyphase FilterRC-CR network that generates I/Q.
I/QIn-phase / QuadratureTwo copies of a signal 90° apart.
IRRImage Rejection RatioHow well an I/Q path suppresses the mirror frequency.
SSBSingle SidebandA frequency shift in one direction only, e.g. the loopback offset.
BPSKBinary Phase-Shift Keying0/180° switching; produces ±f_m sidebands.
VMVector ModulatorI/Q-weighted phase rotator.
RTPSReflection-Type Phase ShifterHybrid coupler terminated by tunable loads.
P1dB1 dB compression pointInput (or output) level where gain drops by 1 dB.
IIP3Input third-order intercept pointLinearity figure; cascades with the gain before each stage.
PAEPower-Added Efficiency(P_out − P_in) / P_DC of a PA.
PsatSaturated output powerMaximum output power of a PA.
DSBDouble SidebandNoise figure counting both sidebands (typical for zero-IF mixers).
PGAProgrammable-Gain AmplifierIF VGA with digitally set gain steps.
AGCAutomatic Gain ControlLoop that sets the VGA gain from the signal level.
HD22nd-order Harmonic Distortion (HD3 = 3rd)Harmonics show up as ghost targets at 2×/3× range.
AM/PMAmplitude-to-phase conversionPhase change caused by amplitude or supply changes.
RLReturn LossMatch quality, in dB.
CplCoupler (directional coupler)Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback.
PDPower DetectorDiode or square-law RF-to-DC converter.
APCAutomatic Power ControlClosed loop from the power detector to the VGA/PA gain code.
DPDDigital PredistortionWideband PA linearisation used in comms; radar uses static gain/phase LUTs instead.
VSWRVoltage Standing-Wave RatioMismatch at the antenna/load; changes the delivered power.
CWContinuous WaveAn unmodulated single-frequency tone.
ENRExcess Noise RatioCalibrated output level of a noise source.
SiGeSilicon-Germanium (BiCMOS)Bipolar-plus-CMOS process used for earlier radar chips.
CMOSComplementary Metal-Oxide-SemiconductorRFCMOS = CMOS process with RF / mmWave capability.
RFCMOSRF-capable CMOSToday's single-chip radar process (e.g. 45/40/28/22 nm).
NMOSN-channel MOS transistor (PMOS = P-channel)
PTATProportional To Absolute TemperatureVoltage or current used by temperature sensors.
BGBandgap referenceTemperature-stable voltage reference (BG1/BG2 = two independent ones).
PVTProcess, Voltage, TemperatureVariation corners a design must cover.

LO, clock & synthesis

Abbr.Stands forNote
PLLPhase-Locked LoopLocks the VCO to the crystal and generates the ramp.
ADPLLAll-Digital PLLPLL with a TDC and a digital loop filter.
VCOVoltage-Controlled Oscillator≈ 19–20.25 GHz, multiplied ×4 to 77 GHz.
PFDPhase-Frequency DetectorCompares the divided VCO with the reference.
CPCharge Pump; also Chip ProbeIn a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test.
TDCTime-to-Digital ConverterDigital phase detector of an ADPLL.
XTALCrystal (reference oscillator)40/50 MHz reference for PLL, ADC and digital.
DDSDirect Digital SynthesizerDigitally generated tone (IF test tone).
KvcoVCO gainTuning sensitivity in MHz/V; varies per band.
AFCAutomatic Frequency Calibration (band calibration)Picks the VCO capacitor-bank band before the PLL closes.
MMDMulti-Modulus DividerProgrammable divider in the PLL feedback, dithered by the ΣΔ modulator.
CMLCurrent-Mode LogicFast differential logic used for the first divider (prescaler) stages at 20 GHz.

Data conversion & digital

Abbr.Stands forNote
SNMStatic Noise MarginNoise an SRAM cell tolerates before flipping; read SNM is the critical one.
SEUSingle-Event UpsetBit flip caused by a particle strike (soft error).
SERSoft-Error RateRate of radiation-induced bit flips, in FIT per Mbit.
MBUMulti-Bit UpsetOne particle flips several neighbouring cells.
RDFRandom Dopant FluctuationRandom number of dopant atoms in a small channel; main cause of Vth mismatch.
LERLine-Edge RoughnessRough gate edges that add Vth variation in small devices.
NPSFNeighbourhood Pattern-Sensitive FaultMemory cell fails only for certain data in its neighbours.
SEC-DEDSingle-Error Correction, Double-Error DetectionECC code used on memory words (e.g. 64 + 8 bits).
ROMRead-Only MemoryMask-programmed memory for boot code and tables.
DRFData-Retention FaultMemory cell loses its value after a pause.
WLWord LineRow select line of a memory array.
BLBit LineColumn data line of a memory array (BL and its complement BLB).
OSROversampling Ratiofs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR.
NTFNoise Transfer FunctionHow a ΣΔ loop shapes quantisation noise out of the signal band.
SNDRSignal-to-Noise-and-Distortion RatioENOB = (SNDR − 1.76) / 6.02.
GBWGain-Bandwidth productOp-amp figure of merit; sets filter and PGA accuracy at IF.
CMRRCommon-Mode Rejection RatioHow well a differential circuit rejects signals common to both inputs.
CSI-2MIPI Camera Serial Interface 2High-speed serial link used for raw radar data.
TSNTime-Sensitive NetworkingDeterministic automotive Ethernet (IEEE 802.1).
ADCAnalog-to-Digital ConverterMain Rx ADCs (ΣΔ) and the aux SAR ADC.
DACDigital-to-Analog ConverterRotator I/Q weights, bias, trim, test-tone generation.
SARSuccessive-Approximation Register ADCSlow, precise ADC used for monitoring.
CTContinuous-Time (CT-ΣΔ)Sigma-delta ADC with a continuous-time loop filter.
ENOBEffective Number of Bits
SFDRSpurious-Free Dynamic RangeTone relative to the largest spur.
THDTotal Harmonic Distortion
DRDynamic Range
INLIntegral NonlinearityDeviation from the ideal transfer line.
DNLDifferential NonlinearityDeviation of each step from 1 LSB.
LSBLeast Significant Bit (MSB = most significant)
DFEDigital Front EndDecimation, DC and I/Q correction, interference handling.
CICCascaded Integrator-CombMultiplier-free decimation filter.
FIRFinite Impulse Response filter
DSPDigital Signal Processor
MCUMicrocontroller Unit
CPUCentral Processing UnitE.g. the RF control CPU that runs chirps and monitors.
SoCSystem-on-Chip
ECUElectronic Control UnitVehicle computer that receives radar data.
SRAMStatic RAM (RAM = random-access memory)
ECCError-Correcting CodeMemory protection for functional safety.
DMADirect Memory Access
LUTLook-Up TableE.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature.
FWFirmware (SW = software)
OTPOne-Time Programmable memoryHolds trims and IDs, like eFuse.
SPISerial Peripheral InterfaceConfiguration / test bus from host or ATE.
CANController Area Network (CAN-FD = Flexible Data-rate)Vehicle bus for object lists.
ETHEthernet (100/1000BASE-T1)Automotive single-pair Ethernet.
CSICamera Serial Interface (MIPI CSI-2)Streams raw radar data to a central SoC.
LVDSLow-Voltage Differential SignalingRaw-data debug / streaming interface.
GPIOGeneral-Purpose Input/Output
IOInput/Output

Power

Abbr.Stands forNote
LDOLow-Dropout regulatorLinear regulator; one per noise-sensitive domain.
PMICPower-Management ICExternal bucks, supervisors and watchdog.
PSRRPower-Supply Rejection RatioHow much supply ripple an LDO (or circuit) blocks.
UVUnder-Voltage (OV = Over-Voltage)Supply monitors, a safety mechanism.
OVOver-VoltageRail above its window; OV monitor protects gate oxides.
PORPower-On ResetHolds the chip in reset until all rails are valid.
BORBrown-Out ResetResets when a supply sags during operation.
ESREquivalent Series ResistanceOf the LDO output capacitor; its zero affects loop stability.
OCPOver-Current ProtectionCurrent limit on a regulator output.
IqQuiescent currentCurrent a regulator draws for itself with no load.
DLDODigital LDOSwitched pass-device array regulated by a comparator loop.
GNDGround

Test & production

Abbr.Stands forNote
EVBEvaluation BoardBoard that carries the chip on the bench with supplies, clock, interfaces and RF transitions.
SMUSource-Measure UnitPrecision instrument that forces voltage or current and measures the other.
OTAOver The AirMeasurement through antennas in a chamber instead of a cable or waveguide.
GSGGround-Signal-Ground probeRF wafer probe with a signal tip between two ground tips.
LRRMLine-Reflect-Reflect-Match calibrationOn-wafer VNA calibration method for mmWave probes.
SCPIStandard Commands for Programmable InstrumentsText command set used to automate instruments.
UPHUnits Per HourTest throughput of a tester and handler.
eFuseElectrically programmable fuseSilicided poly link blown by current; stores trim, ID and repair bits.
MTPMultiple-Time Programmable memorySmall NVM that can be rewritten a few times.
NVMNon-Volatile MemoryKeeps data without power: eFuse, OTP, MTP, flash.
VPPProgramming supply voltageSupply used only to program fuses or OTP.
CRCCyclic Redundancy CheckChecksum that detects corrupted data, e.g. trim words at boot.
RMAReturn Material AuthorizationA customer return, analysed through the 8D process.
8DEight DisciplinesStructured problem solving: team, describe, contain, root cause, correct, verify, prevent, close.
MSAMeasurement System AnalysisProves a measurement is precise and accurate enough (Gage R&R, bias, stability).
GRRGage Repeatability and Reproducibility%GRR < 10 % of tolerance is good.
BISTBuilt-In Self-TestOn-chip stimulus + measurement; result is pass/fail or a value checked against a limit.
BISMBuilt-In Self-MeasurementSame on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend.
DFTDesign for Test
ATEAutomatic Test EquipmentProduction tester.
ATPGAutomatic Test Pattern GenerationScan patterns for digital logic.
IDDQQuiescent supply-current testDetects leakage defects.
PMUParametric Measurement UnitATE DC source/measure channel.
CresContact resistanceProbe or socket contact resistance; measured with the Kelvin or two-current method.
FIMVForce Current, Measure VoltagePMU mode used for open/short (diode) tests.
FVMIForce Voltage, Measure CurrentPMU mode used for leakage and power-short tests.
IILInput leakage current, input Low (IIH = input High)Leakage limit per IO pin, typically |I| < 1 µA.
IIHInput leakage current, input High
ESDElectrostatic DischargePad protection diodes / clamps; the diode method uses them for continuity.
VDDPositive supply rail (VSS = ground / negative rail)
VSSGround / negative supply rail
DCRDC ResistanceE.g. of an RF shunt inductor, 0.5–3 Ω.
Hi-ZHigh impedance (Z)Output driver switched off; the pin floats.
OEOutput EnableControl that switches an output between driving and Hi-Z.
IOZOff-state output leakage (IOZH at VDDIO, IOZL at 0 V)Measured on a pin in Hi-Z; typically |I| < 1–10 µA.
VOHOutput High voltage threshold (VOL = Output Low)Tester comparator levels that decide 1 / Z / 0.
VOLOutput Low voltage threshold
HIGHZIEEE 1149.1 instruction that puts all outputs in Hi-Z
EXTESTIEEE 1149.1 external test instructionBoundary cells drive and sample the pins; used for interconnect and walking-Z tests.
RPCTReduced Pin-Count TestingTesting through JTAG / a few pins, so more sites fit on one tester.
BICSBuilt-In Current SensorOn-chip current monitor for IDDQ per power domain.
SPCStatistical Process Control
VNAVector Network AnalyzerLab instrument for S-parameters.
AWGArbitrary Waveform Generator
DMMDigital Multimeter
GPIBGeneral-Purpose Interface BusInstrument control bus (like LAN).

Safety, standards & regulation

Abbr.Stands forNote
PMHFProbabilistic Metric for random Hardware FailuresISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D.
SEooCSafety Element out of ContextA part developed to ISO 26262 against assumed system requirements.
FMEAFailure Mode and Effects AnalysisQualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage.
FITFailures In TimeFailures per 10⁹ device-hours.
MTTFMean Time To Failure
REDRadio Equipment Directive (EU 2014/53/EU)EU conformity framework for radio transmitters, including radar.
ASILAutomotive Safety Integrity LevelISO 26262 risk class A–D; radar typically ASIL-B.
ISOISO 26262 / ISO/SAE 21434 / ISO 11452Functional safety / cybersecurity / EMC immunity.
FTTIFault-Tolerant Time IntervalTime from fault to hazard; monitors must react within it.
FMEDAFailure Modes, Effects and Diagnostic Analysis
SPFMSingle-Point Fault MetricISO 26262 coverage metric.
LFMLatent Fault MetricISO 26262 coverage metric.
AECAutomotive Electronics Council (AEC-Q100 / Q200)Qualification of ICs / passives.
ETSIEuropean Telecommunications Standards InstituteEN 301 091 / EN 303 396 radar standards.
FCCFederal Communications CommissionUS rules, Part 95M for 76–81 GHz.
EMCElectromagnetic Compatibility
CISPRComité International Spécial des Perturbations RadioélectriquesCISPR 25: vehicle-component emissions.
OOBOut-of-Band (emission)

Digital DFT, stress & reliability

Abbr.Stands forNote
UHSTUnbiased Highly Accelerated Stress TestHAST without bias, 130 °C / 85 % RH; alternative to autoclave.
PTCPower Temperature CyclingTemperature cycling with the device powered on and off.
EDREndurance and Data RetentionQualification of non-volatile memory (AEC-Q100-005).
DPADestructive Physical AnalysisOpening and sectioning parts to inspect their construction and damage.
SEMScanning Electron MicroscopeHigh-magnification imaging of cross-sections and surfaces.
EDXEnergy-Dispersive X-ray spectroscopyElement analysis in the SEM: corrosion, contamination, IMC phases.
FIBFocused Ion BeamPrecise local cutting and imaging; also used for circuit edits.
LTPDLot Tolerance Percent DefectiveDefect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %.
PCPreconditioningBake, moisture soak and reflow before environmental stress (JESD22-A113).
BLRBoard-Level ReliabilityReliability of the package soldered on a PCB (temperature cycling, drop, vibration).
SACTin-Silver-Copper solderLead-free solder alloy (e.g. SAC305) used for balls.
PPAPProduction Part Approval ProcessAutomotive approval package, includes the qualification report.
DRCDesign Rule CheckVerifies layout against foundry manufacturing rules.
LVSLayout Versus SchematicVerifies that the layout matches the schematic netlist.
PEXParasitic ExtractionExtracts resistance, capacitance (and inductance) of the layout for post-layout simulation.
AMSAnalog / Mixed-Signal simulationSimulation that combines transistor-level analog with digital models.
ECOEngineering Change OrderLate design fix; a metal-only ECO changes only upper masks.
SCRSilicon-Controlled RectifierThyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up.
GGNMOSGrounded-Gate NMOSESD clamp that works by parasitic-bipolar snapback.
SEScan EnableSelects shift (SE = 1) or functional capture (SE = 0) in scan flops.
SAFStuck-At FaultNode permanently 0 or 1.
TDFTransition Delay FaultNode slow to rise or fall; needs at-speed test.
STAStatic Timing AnalysisFinds the longest paths for timing-aware ATPG.
OCVOn-Chip VariationTiming derates in STA that account for local (mismatch) variation across the die.
OCCOn-Chip Clock ControllerGates exact launch/capture pulses from the PLL for at-speed test.
LOCLaunch-On-CaptureAt-speed scheme; also called broadside.
LOSLaunch-On-ShiftAt-speed scheme; SE must switch at speed.
EDTEmbedded Deterministic TestScan compression (decompressor + compactor).
LFSRLinear-Feedback Shift RegisterPseudo-random sequence generator.
PRPGPseudo-Random Pattern GeneratorLFSR that feeds the scan chains in LBIST.
MISRMultiple-Input Signature RegisterCompresses responses into one signature.
STUMPSSelf-Test Using MISR and Parallel Shift-register sequence generatorStandard LBIST architecture.
LBISTLogic BISTOn-chip random-pattern scan test; used at key-on.
MBISTMemory BISTOn-chip March-algorithm test of SRAMs.
BIRABuilt-In Redundancy AnalysisComputes which spare rows/columns repair a memory.
BISRBuilt-In Self-RepairLoads the repair from eFuse at boot.
IRIR dropSupply voltage drop (current × resistance), high during scan shift.
JTAGJoint Test Action Group (IEEE 1149.1)Boundary scan and test access port.
TAPTest Access PortJTAG pins TCK, TMS, TDI, TDO, TRST.
BSDLBoundary Scan Description LanguageDescribes a chip's JTAG boundary-scan cells.
IJTAGInternal JTAG (IEEE 1687)Network for accessing on-chip instruments.
MUXMultiplexerSelects one of N inputs; in test, routes sub-block nodes to shared instruments.
ATBAnalog Test BusChip-wide wire pair (force + sense) that test muxes connect sub-block nodes to.
TGTransmission GateParallel NMOS + PMOS switch; passes the full voltage range.
SPDTSingle-Pole Double-Throw switchOne input to one of two outputs (SP4T = one of four).
BBMBreak-Before-MakeSwitching order that opens the old path before closing the new one.
ICLInstrument Connectivity Language (PDL = Procedural Description Language)IJTAG description files.
ECIDElectronic Chip IDUnique per-die ID for traceability.
HVSTHigh-Voltage Stress TestShort over-voltage on the core rail to activate latent oxide defects.
VLVVery-Low-Voltage testTest below nominal V to expose resistive defects.
VminMinimum operating voltageThe pass/fail edge in a shmoo; an outlier Vmin flags a defect.
PATPart Average Testing (AEC-Q001)Outlier limits at robust μ ± 6σ.
DPATDynamic Part Average TestingPAT limits recalculated per lot or wafer.
GDBNGood Die in Bad NeighbourhoodWafer-map screen that rejects dies in defect clusters.
NNRNearest-Neighbour ResidualCompares a die's parameter with its wafer neighbours.
DPPMDefective Parts Per MillionShipped-quality metric; automotive target ≪ 1.
FTFinal TestPackage-level production test.
SLTSystem-Level TestFunctional test by booting the application.
PCMProcess Control MonitorTest structures in the scribe lines, measured by the fab (see WAT).
WATWafer Acceptance TestFab's electrical test of PCM structures before shipping wafers.
OSATOutsourced Semiconductor Assembly and TestCompany that packages and tests the dies.
QAQuality AssuranceSample-based outgoing inspection and audits.
CpProcess capability (Cp)(USL − LSL) / 6σ: spec width vs process spread.
CpkProcess capability indexmin(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67.
USLUpper Spec Limit (LSL = Lower Spec Limit)Design limits; outside them the part is out of spec.
LSLLower Spec Limit
UCLUpper Control Limit (LCL = Lower Control Limit)Process limits from history, usually mean ± 3σ.
LCLLower Control Limit
OCAPOut-of-Control Action PlanDocumented steps when an SPC rule fires.
MRBMaterial Review BoardDecides what happens to held material: release, rework, scrap or deviation.
MIMMetal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal)Precision on-chip capacitors.
MOMMetal-Oxide-Metal (finger) capacitor
BSIMBerkeley Short-channel IGFET ModelIndustry-standard compact transistor model family used in design kits.
VtThreshold voltageGate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD.
IdsatSaturation drain currentId at Vgs = Vds = VDD, per µm of width; transistor strength.
IoffOff-state leakage currentId at Vgs = 0, Vds = VDD.
DIBLDrain-Induced Barrier LoweringVt drop per volt of Vds in short-channel devices.
SSSubthreshold swing (also SS = slow-slow process corner)mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature.
TTTypical-typical process cornerFF = fast-fast; FS / SF = skewed NMOS / PMOS corners.
FFFast-fast process corner
gmTransconductance∂Id/∂Vgs; the transistor's gain.
gdsOutput conductance∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds).
CoxGate-oxide capacitance per areaεox / Tox.
ToxGate-oxide thicknessMeasured with C-V structures in WAT.
fTTransit (unity current-gain) frequency≈ gm / 2π(Cgs + Cgd).
fmaxMaximum oscillation (unity power-gain) frequencyNeeds ≈ 3–4× the operating frequency for useful gain.
VbdGate-oxide breakdown voltageVoltage where oxide current jumps past compliance in a V-ramp test.
BVBreakdown VoltageBVdss = drain-source (gate off), BVj = junction.
BVdssDrain-source breakdown voltageTransistor off-state breakdown; limits PA drain swing.
BVjJunction breakdown voltageReverse breakdown of N+/P-well or P+/N-well diodes.
TLPTransmission-Line PulseESD device characterisation with short, high-current pulses.
QBDCharge to breakdownTotal charge an oxide passes before breaking down (reliability).
IMDInter-Metal DielectricInsulator between metal lines/layers; tested with comb structures.
CMPChemical-Mechanical PlanarizationPolishing step that flattens each layer; source of centre, edge and ring signatures.
OPCOptical Proximity CorrectionMask shape corrections; weak spots (hotspots) can fail per reticle shot.
EBREdge Bead RemovalRemoves resist build-up at the wafer edge.
D0Defect densityRandom defects per unit area; baseline yield Y ≈ e^(−D0·A).
HTOLHigh-Temperature Operating Life≈ 1000 h biased at max temperature (AEC-Q100).
ELFREarly Life Failure RateShort high-temperature operation of a large sample.
TCTemperature CyclingPackage and interconnect fatigue test.
THBTemperature-Humidity-Bias85 °C / 85% RH with bias.
HASTHighly Accelerated Stress Test130 °C / 85% RH with bias.
RHRelative Humidity
HTSLHigh-Temperature Storage LifeUnbiased bake.
HBMHuman-Body Model (ESD)
CDMCharged-Device Model (ESD)
LULatch-UpJESD78 test.
EMElectromigrationMetal wear-out under current (wafer-level reliability).
TDDBTime-Dependent Dielectric BreakdownGate-oxide wear-out.
HCIHot-Carrier InjectionTransistor degradation mechanism.
NBTINegative-Bias Temperature InstabilityPMOS threshold drift.

PCB, package & materials

Abbr.Stands forNote
TCBThermo-Compression BondingFlip-chip attach with heat and force per die; fine pitch, low warpage.
MUFMolded UnderfillMold compound that also fills the gap under a flip-chip die.
CSAMC-mode Scanning Acoustic MicroscopyUltrasound imaging of voids and delamination inside packages.
AOIAutomated Optical InspectionCamera inspection of RDL, bumps and balls in the assembly line.
KGDKnown-Good DieDie that passed wafer sort and is released for assembly.
WLPWafer-Level PackagePackage built on the whole wafer (fan-in) or a reconstituted wafer (fan-out).
PCBPrinted Circuit Board
RDLRedistribution LayerThin-film Cu wiring that routes die pads to balls (fan-out) or bumps.
UBMUnder-Bump MetallisationMetal stack between die/RDL pad and the solder.
FOWLPFan-Out Wafer-Level PackageDie embedded in mold with RDL fanning out to balls; eWLB is one type.
CSPChip-Scale PackagePackage only slightly larger than the die (FC-CSP = flip-chip CSP).
AiPAntenna-in-PackageAntennas built into package layers.
IMCIntermetallic CompoundLayer formed between solder and UBM/pad; grows with time and temperature.
CTECoefficient of Thermal ExpansionMismatch between materials drives solder and bump fatigue.
MSLMoisture Sensitivity LevelJ-STD-020 rating: how long a package may sit out of dry pack before reflow.
ELKExtreme Low-k dielectricFragile back-end dielectric in advanced nodes; cracks under bump stress.
NSMDNon-Solder-Mask-Defined padPCB pad style that improves solder-joint fatigue life.
DkDielectric constantSets line impedance and antenna tuning; shifts with moisture.
DfDissipation factorDielectric loss; key for RF loss at 77 GHz.
C-SAMC-mode Scanning Acoustic MicroscopyNon-destructive imaging of delamination and voids.
PBOPolybenzoxazolePolymer dielectric used in RDL (like polyimide).
EOSElectrical OverstressDamage from overvoltage or overcurrent beyond ESD events.
BGABall Grid ArrayFC-BGA = flip-chip BGA.
eWLBembedded Wafer-Level Ball-grid-arrayFan-out package with low RF loss.
AoPAntenna-on-Package
LoPLaunch-on-PackageRF launched from package into waveguide / antenna.
GCPWGrounded Coplanar WaveguidePCB transmission line at the ball launch.
SIWSubstrate-Integrated WaveguideWaveguide formed with via fences in the PCB.
FR4Flame-Retardant epoxy-glass laminateStandard low-cost PCB material.
ENEPIGElectroless Nickel, Electroless Palladium, Immersion GoldPCB surface finish.
ImAgImmersion SilverPCB surface finish.
HASLHot-Air Solder LevelingSurface finish; too rough/uneven for 77 GHz.
PBTPolybutylene terephthalate (PC = polycarbonate)Radome plastics.
HFSSHigh-Frequency Structure Simulator (Ansys)3D EM simulator (CST = Dassault's equivalent).