Frequency Synthesizer (PLL)

Frequency synthesizer: PLL, VCO and chirp generation

LO · 20 → 77 GHz

The synthesizer is the heart of an FMCW radar: it makes the chirp. A fractional-N PLL locks a ~20 GHz VCO to a 40 MHz crystal and steps its division ratio every few nanoseconds so the frequency ramps linearly; a ×4 multiplier then brings the chirp to 76–81 GHz for the Tx and the Rx mixers. Its phase noise, ramp linearity and spurs set how close and how small a target the radar can still see (see the signal-chain overview).

Fractional-N PLL for FMCW. Forward path: reference → PFD → charge pump → loop filter → VCO. Feedback: the multi-modulus divider (MMD) divides the VCO by N; a ΣΔ modulator dithers N between integers to get a fractional average, and the ramp generator changes that average every cycle to sweep the frequency. Band calibration (AFC) picks the VCO capacitor-bank band before the loop closes; the lock detector watches the PFD pulses.

Inside the blocks: charge pump, loop filter, LC tank, ×4

The loop diagram hides the circuits that set the synthesizer's performance. These are the four that matter most, each drawn at transistor or component level with the equations that tie it to the loop.

Charge pump + loop filter

The charge pump turns the PFD's UP/DN pulses into current packets; the loop filter integrates them into Vtune. R1·C1 adds the zero that makes the loop stable, C2 smooths the ripple of each pulse, and R3·C3 is an extra pole that suppresses reference spurs.

Open-loop gain (type-II): G(s) = (I_CP / 2π) · Z_LF(s) · (2π·Kvco / s) / N Zero: ω_z = 1 / (R1·C1) Pole: ω_p2 ≈ 1 / (R1·C2) (C1 ≫ C2) Loop bandwidth (approx.): ω_c ≈ I_CP · R1 · 2π·Kvco / (2π·N) Design for ω_z ≈ ω_c / 4, ω_p2 ≈ 4·ω_c → phase margin ≈ 50–60°

UP/DN current mismatch and switch charge injection leave a net charge every reference cycle, even when locked, which appears as reference spurs; matched sources and dummy switches reduce it.
Leakage on the V_cp / Vtune node (switch Ioff, varactor gate) must be replaced every cycle, adding another spur source.
Kvco changes per band, so I_CP is often programmable to keep ω_c constant across bands.
Loop-filter resistors add thermal noise and the capacitors take large area; C1 is usually the biggest capacitor on the synthesizer.

VCO: cross-coupled LC tank

The tank (inductor L, varactors, switched capacitor bank and parasitics) sets the frequency; the cross-coupled pair M1/M2 provides the negative resistance that sustains oscillation; the tail current sets the amplitude. Coarse tuning uses the band code, fine tuning uses Vtune on the varactors.

f0 = 1 / (2π·√(L · C_total)) C_total = C_fixed + C_var(Vtune) + Σ C_bank,k + C_par Tank Q: 1/Q = 1/Q_L + 1/Q_C (switch R_on lowers Q_C) Start-up: gm(M1,M2) · R_p ≥ 2–3, R_p = Q · ω0 · L Swing: V_tank ≈ (4/π) · I_tail · R_p (current-limited), capped by VDD and oxide stress

Inductor: a top-metal spiral or single turn, ≈ 100–300 pH at 20 GHz; its Q (≈ 15–25) usually dominates phase noise.
Varactors: accumulation-mode MOS for good Cmax/Cmin; a larger varactor gives more fine-tuning range but raises Kvco and noise sensitivity.
Capacitor bank: binary-weighted MOM capacitors with switch transistors; wide switches lower R_on (better Q) but add off-state capacitance (less range). This trade-off sets the number of bands.
Tail current: sets the swing; a tail filter (or no tail, with a resistor) reduces flicker-noise up-conversion into close-in phase noise.

Buffer + ×4 multiplier

Two cascaded push-push doublers take the 20 GHz VCO to 80 GHz. In each doubler, two transistors driven in anti-phase share a load tuned at 2f: the fundamental currents cancel and the second-harmonic currents add. Tuned amplifiers between stages restore the level and filter unwanted harmonics. Some designs use a ~38.5 GHz VCO with a single doubler instead.

Why ×4 instead of a 77 GHz VCO: a 20 GHz tank has much higher Q (lower phase noise), wider tuning range, and easier dividers; the price is +12 dB phase noise through the multiplier and the multiplier's power and area.
Buffer: isolates the tank from the multiplier load, so drive changes don't pull the VCO frequency.
Harmonic suppression: leftover f, 3f and 5f components become spurs at the Tx; typically kept below −30 dBc by the push-push symmetry plus tuned loads.
Drive level: each doubler needs enough input swing (see the swing table below); too little drive lowers the 77 GHz LO power to the PA and mixers.

Frequency plan

f_VCO = N.frac × f_ref f_RF = 4 × f_VCO f_ref = 40 MHz → N = 475 … 506.25 for f_VCO = 19.0 … 20.25 GHz (RF 76 … 81 GHz) ΣΔ step (24-bit fraction): f_ref / 2^24 ≈ 2.4 Hz VCO slope = RF slope / 4 e.g. 100 MHz/µs at 77 GHz → 25 MHz/µs at the VCO Phase noise: L_RF = L_VCO + 20·log10(4) = L_VCO + 12 dB

How it locks

Power-up and reference: the crystal starts (ms) and the LDOs settle; the VCO starts oscillating once its core gain exceeds the tank loss (below).
Coarse tuning, band calibration (AFC): with the loop open and Vtune held at mid-range, a counter compares the divided VCO with the reference and a binary search sets the capacitor-bank code. This brings the VCO within one band (typically tens of µs).
Fine tuning, phase lock: the loop closes. The PFD compares REF and DIV edges and outputs UP or DN pulses as wide as the phase error; the charge pump turns them into current, the loop filter into Vtune, and the VCO moves until the edges align. The lock detector declares lock when the UP/DN pulse width stays inside a small window for many cycles (a few µs to tens of µs).
Ramp tracking: during a chirp the loop must follow N changing every cycle. Tracking error grows with the slope and falls with loop bandwidth; fast chirps add two-point modulation (a feed-forward step injected at the VCO as well as the divider) or pre-distorted ramps.
Reset between chirps: the ramp jumps back; the loop must re-settle during the idle time before the ADC samples the next chirp.

Tri-state PFD while pulling into lock. REF leads DIV, so UP is on for the phase difference and the charge pump raises Vtune; each cycle the difference shrinks. Both outputs always pulse briefly (the reset), which keeps the charge pump out of the "dead zone" where tiny errors would produce no correction.

VCO design

Topology: an LC oscillator, usually a cross-coupled NMOS (or CMOS) pair driving a tank of an on-chip inductor, MOS varactors (fine tuning by Vtune) and a switched-capacitor bank (coarse bands). A tail current source or resistor sets the bias.
Start-up condition: the pair's negative resistance must cancel the tank loss with margin: gm · Rp ≥ 2–3, where Rp = Q·ω·L is the tank's parallel loss resistance. Check at the slow corner and hot, where gm is lowest and Q may drop.
Tuning range: the bands must cover 19.0–20.25 GHz at every process corner and temperature, so the design target is wider, typically about 18–21.5 GHz (≈ 17 %), with neighbouring bands overlapping by 10–20 %.
Kvco: sensitivity in MHz/V, typically a few hundred MHz/V per band. High Kvco makes the loop sensitive to Vtune noise and spurs; low Kvco needs more bands and more cap-bank switches (which lower Q). Kvco varies across bands, so the loop gain and bandwidth are compensated per band.
Phase noise (Leeson): L(Δf) ≈ 10·log[(2FkT/Ps)·(1 + (f0 / (2·Q·Δf))²)·(1 + fc/Δf)]. Higher tank Q and higher signal power lower it; flicker noise of the core (fc) adds close-in noise.
Amplitude: an amplitude control loop keeps the swing large enough for low phase noise and to drive the buffers, but below the level that stresses the varactors and gate oxides.

Illustrative tuning curves, not a real design. Eight capacitor-bank bands, each tuning about 0.55 GHz over the usable Vtune range of 0.2–1.1 V (limited by the charge-pump output compliance), overlapping their neighbours so there is no gap at any corner. Band calibration picks the band whose curve crosses the wanted frequency near mid-Vtune, leaving room for temperature drift after lock.

Voltage swings and minimum levels

Node	Typical requirement	Why a minimum (and a maximum)
VCO tank swing	≈ 1.0–1.6 Vpp differential	Minimum: phase noise and buffer drive. Maximum: varactor and gate-oxide stress (reliability), AM-to-PM conversion
VCO buffer → first divider stage	≥ 0.2–0.4 Vpp differential at 20 GHz	Current-mode-logic (CML) prescalers have an input-sensitivity curve: below the minimum swing they miscount or free-run
Buffer → ×4 multiplier	≈ 0.6–1 Vpp differential	Multiplier conversion gain and harmonic suppression depend on drive; too little drive lowers the 77 GHz LO
Vtune (charge-pump output)	≈ 0.2 V … VDD − 0.2 V	Outside the compliance range the CP current sources lose headroom, UP/DN mismatch grows and spurs rise; band cal keeps Vtune near the middle
Reference input	≈ 0.3–1 Vpp (clipped sine or CMOS)	Low slew adds jitter to the PFD edges
Supply of the VCO LDO	tens of µV ripple	Supply pushing (MHz/V) converts ripple into FM and spurs (power section)

Key specifications (typical)

Parameter	Typical target
Reference	40–50 MHz crystal, low jitter
VCO range / bands	≈ 18–21.5 GHz design, 16–64 cap-bank codes
Kvco	≈ 200–600 MHz/V per band
Charge-pump current	≈ 0.1–1 mA, UP/DN mismatch < 1–2 %
Loop bandwidth	≈ 1–3 MHz (wide, to track fast ramps)
Phase noise @ 1 MHz	≈ −102…−107 dBc/Hz at 20 GHz → −90…−95 dBc/Hz at 77 GHz
Lock time	band cal ≈ 10–50 µs; phase lock ≈ 5–30 µs
Ramp	slope up to ≈ 100–250 MHz/µs at RF; RMS nonlinearity < 0.1 % of bandwidth
Spurs	reference and fractional spurs < −60…−70 dBc

Issues and failure modes

Issue	Symptom in the radar	Typical cause	Fix / how it's caught
Won't lock / out of range	No chirp, lock-detect fault	Tuning range doesn't cover the target at a corner or temperature; band cal picks a wrong band	Design range margin; BIST path D checks band edges at test; band-code distribution per lot. Full debug flow: why it won't lock
VCO fails to start	No LO at power-up	gm·Rp too low at slow corner, hot, low supply	Start-up margin ≥ 2–3 at SS/hot; test at low V and hot
Divider miscount	Wrong frequency, lock at a false ratio	Buffer swing below the prescaler's input sensitivity at a corner	Swing margin; counter check of the output frequency
Cycle slips during fast chirps	Frequency jumps, ghost targets, smeared range	Ramp slope too fast for the loop bandwidth; ramp start transient	Two-point modulation, wider loop, longer idle time
Reference spurs	Ghost targets at fixed range	Charge-pump UP/DN mismatch and leakage ripple Vtune every reference cycle	CP matching, low-leakage switches, loop-filter design; spur check via loopback FFT
Fractional spurs	Spurs that move with the chirp frequency	ΣΔ quantisation noise folded by nonlinearity in the PFD/CP	Higher-order ΣΔ, dithering, CP linearisation
High phase noise	Weak targets hidden near strong ones	Low inductor Q, CP / loop-filter resistor noise, supply noise	Tank Q, loop optimisation, VCO LDO PSRR
Ramp nonlinearity	Range blur, higher sidelobes	Kvco variation along the ramp, loop tracking error	Pre-distortion LUT from the PLL phase-error monitor (BISM)
VCO pulling / pushing	FM and spurs that follow Tx on/off	PA or ×4 coupling back into the tank; supply ripple	Buffers and isolation, layout separation, supply filtering
Drift after lock	Loss of lock as temperature changes during operation	Vtune walks to its limit because the band was chosen at the edge	Choose the band near mid-Vtune; re-run band cal between frames

Why it won't lock: causes and debug flow

A PLL locks only if every link in the loop works: a reference, a running VCO that can reach the target frequency, a divider that counts correctly, a correction with the right sign and enough charge-pump headroom, a stable loop, and a lock detector that judges correctly. "Sometimes it doesn't lock" almost always means one of these links is marginal at a corner, a temperature or a supply level. Two on-chip readings find the broken link quickly: Vtune through the analog test mux, and the divided VCO frequency from the frequency counter.

What locking needs	What breaks it	Symptom	How to check on chip
1. Reference present and clean	Crystal not started, low amplitude or slow edges, wrong reference divider	No PFD activity, or random lock	Count the reference through the clock-observe mux
2. VCO oscillates	gm·Rp too low at slow corner, hot or low supply; VCO LDO not up yet	No output; counter reads 0	Counter; VCO bias current through the test mux
3. VCO can reach the target	Tuning range too narrow at a corner or temperature; band cal picked a wrong band (miscount, or done at another temperature); gap between bands	Vtune stuck at a rail	Open loop: count each band at Vtune min and max
4. Divider counts correctly	Buffer swing below prescaler sensitivity; wrong N or fractional word; ΣΔ overflow; multi-modulus divider timing	Locks at the wrong frequency (false ratio), or Vtune railed	Counter on the output vs expected; check swing at the corner
5. Correction has the right sign, CP has headroom	UP/DN swapped (design bug or PFD reset race); CP out of compliance; leakage larger than CP current	Vtune runs to the opposite rail	Force a small offset in N and watch which way Vtune moves
6. Loop is stable	Kvco much higher than designed on one band or corner; wrong CP current code; loop-filter R/C off target	Vtune oscillates; lock detect toggles	Log Vtune or PLL phase error over time; check per-band CP scaling
7. Loop is fast enough to follow	Chirp slope too steep for the loop bandwidth; ramp starts too soon after reset	Locks on CW, loses lock during chirps (cycle slips)	PLL phase-error monitor along the ramp; lengthen the idle time
8. Lock detector judges correctly	Window too tight for the ΣΔ phase noise; count window too short	Frequency is right but lock detect says no	Compare lock-detect flag with the counter result
9. It stays locked	Band chosen near the Vtune edge and temperature drifts; supply ripple; PA or ×4 pulling the VCO	Locks at start-up, drops after warm-up or when Tx turns on	Read Vtune after lock; re-run band cal between frames

What Vtune does after the loop closes tells you where to look. A rail means the VCO can't reach the target (range, band, divider) or the correction has the wrong sign; an oscillation means the loop is unstable; a steady mid-range Vtune with no lock flag points to the divider ratio or the lock detector.

Reference: count it through the clock-observe mux.
Open loop: hold Vtune at its minimum and maximum and count the VCO in every band. This gives the real tuning curves and shows whether the target is inside a band with margin.
Close the loop and read Vtune: compare with the four patterns above.
Counter on the output: a clean lock at the wrong frequency means the divider or its settings.
Repeat at the edges: slow corner, hot and cold, minimum supply. Most intermittent failures only show there.

Why only sometimes? Band cal done cold and then the chip warms up (or the reverse); a VCO or prescaler that just meets its margin at one corner; supply noise during band cal making the counter pick the neighbouring band; band cal starting before the LDO or reference has settled; and Tx turning on and pulling the VCO. Choosing the band near mid-Vtune, waiting for supplies before band cal, and re-running band cal between frames remove most of them.

PCM / WAT items that matter for the synthesizer

PCM / WAT item	Block	Effect
Inductor L and Q (RF structures), top-metal thickness and sheet resistance	VCO tank	Centre frequency, phase noise, start-up margin (Rp = Q·ω·L)
Varactor C-V (Cmax/Cmin, Q)	VCO fine tuning	Kvco, tuning range per band, phase noise
MIM / MOM capacitance density	Cap bank, loop filter	Band positions and overlap; loop bandwidth and stability
NMOS gm, Idsat, fT	VCO core, CML prescaler, buffers	Start-up margin, maximum divider speed, output swing
Vt (lin / sat)	CML divider, charge pump	Headroom and compliance range of Vtune
Poly / diffusion sheet resistance	Loop-filter resistor, bias	Loop bandwidth and damping; resistor thermal noise
Ioff, junction leakage	Charge-pump switches, loop filter node	Leakage on Vtune → reference spurs
Matching (Pelgrom pairs)	Charge-pump UP/DN current sources	UP/DN mismatch → reference spurs

A lot-level shift in these WAT items shows up first in the band-calibration code distribution: if the chosen codes drift toward one end of the bank, the tuning range margin is being used up (see PCM / WAT & SPC).

Frequency-plan calculator

VCO range needed

–

Divide ratio N

Tuning range needed / designed

Margin below / above

Slope at the VCO

N change per reference cycle

Glossary of abbreviations

Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.

Radar system & ADAS

Abbr.	Stands for	Note
FCW	Forward Collision Warning	Warns of an imminent frontal collision; stage before AEB.
FCTA	Front Cross-Traffic Alert	Front corner-radar function at junctions and driveways.
RCTB	Rear Cross-Traffic Braking	Brakes automatically when RCTA detects cross traffic while reversing.
DOW	Door-Opening Warning	Warns before a door is opened into an approaching cyclist or car.
VRU	Vulnerable Road User	Pedestrians, cyclists and motorcyclists.
TTC	Time To Collision	Range divided by closing speed; triggers warnings and braking.
LRR	Long-Range Radar	Front radar, ≈ 200–300 m, narrow field of view.
MRR	Mid-Range Radar	≈ 80–160 m, ±40–60° field of view.
SRR	Short-Range Radar	Corner radar, ≈ 30–80 m, ±75–90° field of view.
NCAP	New Car Assessment Programme	Consumer safety ratings (Euro NCAP, C-NCAP, IIHS …).
GSR	General Safety Regulation (EU) 2019/2144	Makes AEB and other assistance functions mandatory in the EU.
CPD	Child Presence Detection	In-cabin sensing (often 60 GHz radar) that detects a child left in the car.
ACC	Adaptive Cruise Control	Keeps distance to the car ahead; uses long-range front radar.
ADAS	Advanced Driver-Assistance Systems	The vehicle functions the radar serves.
AEB	Autonomous Emergency Braking	Brakes automatically when a collision is imminent.
BSD	Blind-Spot Detection	Corner-radar function.
LCA	Lane-Change Assist	Corner-radar function that warns of fast approaching vehicles.
RCTA	Rear Cross-Traffic Alert	Rear corner-radar function when reversing.
L2	SAE automation Level 2 (L3 = Level 3)	Partial (L2) and conditional (L3) driving automation.
FMCW	Frequency-Modulated Continuous Wave	A linear chirp; range comes from the beat frequency f_b = S·2R/c.
FoV	Field of View	Angular coverage in azimuth and elevation.
RCS	Radar Cross Section	Target reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0).
dBsm	Decibels relative to 1 m²	Unit of RCS.
EIRP	Effective Isotropic Radiated Power	Tx power + antenna gain; limited by regulations.
MIMO	Multiple-Input Multiple-Output	N_tx × N_rx channels form a larger virtual array.
TDM	Time-Division Multiplexing	One Tx per chirp; v_max falls by a factor of N_tx.
BPM	Binary Phase Modulation	0/180° codes across chirps separate the Tx signals.
DDMA	Doppler-Division Multiple Access	Each Tx gets a slow-time phase ramp and separates in Doppler.
DoA	Direction of Arrival	Angle estimation over the virtual array.
DBF	Digital Beamforming	FFT or matched steering over array channels.
CFAR	Constant False Alarm Rate	Adaptive detection threshold (CA = cell-averaging, OS = ordered-statistic).
FFT	Fast Fourier Transform	Range, Doppler and angle FFTs build the radar cube.
SNR	Signal-to-Noise Ratio
MUSIC	MUltiple SIgnal Classification	Subspace super-resolution DoA algorithm.
ESPRIT	Estimation of Signal Parameters via Rotational Invariance Techniques	Super-resolution DoA algorithm.
IAA	Iterative Adaptive Approach	Super-resolution spectral / DoA estimator.
DBSCAN	Density-Based Spatial Clustering of Applications with Noise	Groups detections into objects.
EKF	Extended Kalman Filter	Nonlinear tracking filter.
UKF	Unscented Kalman Filter	Nonlinear tracking filter using sigma points.
IMM	Interacting Multiple Model	Tracker that mixes several motion models.
HWA	Hardware Accelerator	On-chip FFT / radar processing engine.
RTS	Radar Target Simulator	Echo generator for HIL and EOL testing.
HIL	Hardware-in-the-Loop	Testing the real sensor against simulated scenarios.
EOL	End-of-Line	Final production test of a module or vehicle.

RF & analog front end

Abbr.	Stands for	Note
HPBW	Half-Power Beamwidth	Angle between the −3 dB points of an antenna or array beam.
PDN	Power Delivery Network	Regulators, planes, decoupling and package paths that supply the chip.
PI	Power Integrity	Keeping supply voltage within limits under load steps and noise.
EMI	Electromagnetic Interference	Unwanted emission or pick-up of electromagnetic energy.
BCI	Bulk Current Injection	Immunity test (ISO 11452-4) that injects RF current into a cable harness.
TIM	Thermal Interface Material	Gap pad or paste between board or package and the heat sink.
RF	Radio Frequency	Here the 76–81 GHz signal.
LO	Local Oscillator	The chirp signal that drives the Tx and the Rx mixers.
IF	Intermediate Frequency	The beat / baseband signal after the mixer, DC–20 MHz.
PA	Power Amplifier	Tx output stage, 12–14 dBm.
LNA	Low-Noise Amplifier	First Rx stage; sets most of the NF.
NF	Noise Figure	Noise the receiver adds, in dB.
VGA	Variable-Gain Amplifier	Programmable-gain stage (IF), or signed VGAs in the phase rotator.
TIA	Transimpedance Amplifier	Current-to-voltage stage after a passive mixer.
HPF	High-Pass Filter	In IF: removes leakage and DC, and equalises R⁻⁴.
LPF	Low-Pass Filter
AAF	Anti-Aliasing Filter	Low-pass filter in front of the ADC.
PPF	Polyphase Filter	RC-CR network that generates I/Q.
I/Q	In-phase / Quadrature	Two copies of a signal 90° apart.
IRR	Image Rejection Ratio	How well an I/Q path suppresses the mirror frequency.
SSB	Single Sideband	A frequency shift in one direction only, e.g. the loopback offset.
BPSK	Binary Phase-Shift Keying	0/180° switching; produces ±f_m sidebands.
VM	Vector Modulator	I/Q-weighted phase rotator.
RTPS	Reflection-Type Phase Shifter	Hybrid coupler terminated by tunable loads.
P1dB	1 dB compression point	Input (or output) level where gain drops by 1 dB.
IIP3	Input third-order intercept point	Linearity figure; cascades with the gain before each stage.
PAE	Power-Added Efficiency	(P_out − P_in) / P_DC of a PA.
Psat	Saturated output power	Maximum output power of a PA.
DSB	Double Sideband	Noise figure counting both sidebands (typical for zero-IF mixers).
PGA	Programmable-Gain Amplifier	IF VGA with digitally set gain steps.
AGC	Automatic Gain Control	Loop that sets the VGA gain from the signal level.
HD2	2nd-order Harmonic Distortion (HD3 = 3rd)	Harmonics show up as ghost targets at 2×/3× range.
AM/PM	Amplitude-to-phase conversion	Phase change caused by amplitude or supply changes.
RL	Return Loss	Match quality, in dB.
Cpl	Coupler (directional coupler)	Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback.
PD	Power Detector	Diode or square-law RF-to-DC converter.
APC	Automatic Power Control	Closed loop from the power detector to the VGA/PA gain code.
DPD	Digital Predistortion	Wideband PA linearisation used in comms; radar uses static gain/phase LUTs instead.
VSWR	Voltage Standing-Wave Ratio	Mismatch at the antenna/load; changes the delivered power.
CW	Continuous Wave	An unmodulated single-frequency tone.
ENR	Excess Noise Ratio	Calibrated output level of a noise source.
SiGe	Silicon-Germanium (BiCMOS)	Bipolar-plus-CMOS process used for earlier radar chips.
CMOS	Complementary Metal-Oxide-Semiconductor	RFCMOS = CMOS process with RF / mmWave capability.
RFCMOS	RF-capable CMOS	Today's single-chip radar process (e.g. 45/40/28/22 nm).
NMOS	N-channel MOS transistor (PMOS = P-channel)
PTAT	Proportional To Absolute Temperature	Voltage or current used by temperature sensors.
BG	Bandgap reference	Temperature-stable voltage reference (BG1/BG2 = two independent ones).
PVT	Process, Voltage, Temperature	Variation corners a design must cover.

LO, clock & synthesis

Abbr.	Stands for	Note
PLL	Phase-Locked Loop	Locks the VCO to the crystal and generates the ramp.
ADPLL	All-Digital PLL	PLL with a TDC and a digital loop filter.
VCO	Voltage-Controlled Oscillator	≈ 19–20.25 GHz, multiplied ×4 to 77 GHz.
PFD	Phase-Frequency Detector	Compares the divided VCO with the reference.
CP	Charge Pump; also Chip Probe	In a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test.
TDC	Time-to-Digital Converter	Digital phase detector of an ADPLL.
XTAL	Crystal (reference oscillator)	40/50 MHz reference for PLL, ADC and digital.
DDS	Direct Digital Synthesizer	Digitally generated tone (IF test tone).
Kvco	VCO gain	Tuning sensitivity in MHz/V; varies per band.
AFC	Automatic Frequency Calibration (band calibration)	Picks the VCO capacitor-bank band before the PLL closes.
MMD	Multi-Modulus Divider	Programmable divider in the PLL feedback, dithered by the ΣΔ modulator.
CML	Current-Mode Logic	Fast differential logic used for the first divider (prescaler) stages at 20 GHz.

Data conversion & digital

Abbr.	Stands for	Note
SNM	Static Noise Margin	Noise an SRAM cell tolerates before flipping; read SNM is the critical one.
SEU	Single-Event Upset	Bit flip caused by a particle strike (soft error).
SER	Soft-Error Rate	Rate of radiation-induced bit flips, in FIT per Mbit.
MBU	Multi-Bit Upset	One particle flips several neighbouring cells.
RDF	Random Dopant Fluctuation	Random number of dopant atoms in a small channel; main cause of Vth mismatch.
LER	Line-Edge Roughness	Rough gate edges that add Vth variation in small devices.
NPSF	Neighbourhood Pattern-Sensitive Fault	Memory cell fails only for certain data in its neighbours.
SEC-DED	Single-Error Correction, Double-Error Detection	ECC code used on memory words (e.g. 64 + 8 bits).
ROM	Read-Only Memory	Mask-programmed memory for boot code and tables.
DRF	Data-Retention Fault	Memory cell loses its value after a pause.
WL	Word Line	Row select line of a memory array.
BL	Bit Line	Column data line of a memory array (BL and its complement BLB).
OSR	Oversampling Ratio	fs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR.
NTF	Noise Transfer Function	How a ΣΔ loop shapes quantisation noise out of the signal band.
SNDR	Signal-to-Noise-and-Distortion Ratio	ENOB = (SNDR − 1.76) / 6.02.
GBW	Gain-Bandwidth product	Op-amp figure of merit; sets filter and PGA accuracy at IF.
CMRR	Common-Mode Rejection Ratio	How well a differential circuit rejects signals common to both inputs.
CSI-2	MIPI Camera Serial Interface 2	High-speed serial link used for raw radar data.
TSN	Time-Sensitive Networking	Deterministic automotive Ethernet (IEEE 802.1).
ADC	Analog-to-Digital Converter	Main Rx ADCs (ΣΔ) and the aux SAR ADC.
DAC	Digital-to-Analog Converter	Rotator I/Q weights, bias, trim, test-tone generation.
SAR	Successive-Approximation Register ADC	Slow, precise ADC used for monitoring.
CT	Continuous-Time (CT-ΣΔ)	Sigma-delta ADC with a continuous-time loop filter.
ENOB	Effective Number of Bits
SFDR	Spurious-Free Dynamic Range	Tone relative to the largest spur.
THD	Total Harmonic Distortion
DR	Dynamic Range
INL	Integral Nonlinearity	Deviation from the ideal transfer line.
DNL	Differential Nonlinearity	Deviation of each step from 1 LSB.
LSB	Least Significant Bit (MSB = most significant)
DFE	Digital Front End	Decimation, DC and I/Q correction, interference handling.
CIC	Cascaded Integrator-Comb	Multiplier-free decimation filter.
FIR	Finite Impulse Response filter
DSP	Digital Signal Processor
MCU	Microcontroller Unit
CPU	Central Processing Unit	E.g. the RF control CPU that runs chirps and monitors.
SoC	System-on-Chip
ECU	Electronic Control Unit	Vehicle computer that receives radar data.
SRAM	Static RAM (RAM = random-access memory)
ECC	Error-Correcting Code	Memory protection for functional safety.
DMA	Direct Memory Access
LUT	Look-Up Table	E.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature.
FW	Firmware (SW = software)
OTP	One-Time Programmable memory	Holds trims and IDs, like eFuse.
SPI	Serial Peripheral Interface	Configuration / test bus from host or ATE.
CAN	Controller Area Network (CAN-FD = Flexible Data-rate)	Vehicle bus for object lists.
ETH	Ethernet (100/1000BASE-T1)	Automotive single-pair Ethernet.
CSI	Camera Serial Interface (MIPI CSI-2)	Streams raw radar data to a central SoC.
LVDS	Low-Voltage Differential Signaling	Raw-data debug / streaming interface.
GPIO	General-Purpose Input/Output
IO	Input/Output

Power

Abbr.	Stands for	Note
LDO	Low-Dropout regulator	Linear regulator; one per noise-sensitive domain.
PMIC	Power-Management IC	External bucks, supervisors and watchdog.
PSRR	Power-Supply Rejection Ratio	How much supply ripple an LDO (or circuit) blocks.
UV	Under-Voltage (OV = Over-Voltage)	Supply monitors, a safety mechanism.
OV	Over-Voltage	Rail above its window; OV monitor protects gate oxides.
POR	Power-On Reset	Holds the chip in reset until all rails are valid.
BOR	Brown-Out Reset	Resets when a supply sags during operation.
ESR	Equivalent Series Resistance	Of the LDO output capacitor; its zero affects loop stability.
OCP	Over-Current Protection	Current limit on a regulator output.
Iq	Quiescent current	Current a regulator draws for itself with no load.
DLDO	Digital LDO	Switched pass-device array regulated by a comparator loop.
GND	Ground

Test & production

Abbr.	Stands for	Note
EVB	Evaluation Board	Board that carries the chip on the bench with supplies, clock, interfaces and RF transitions.
SMU	Source-Measure Unit	Precision instrument that forces voltage or current and measures the other.
OTA	Over The Air	Measurement through antennas in a chamber instead of a cable or waveguide.
GSG	Ground-Signal-Ground probe	RF wafer probe with a signal tip between two ground tips.
LRRM	Line-Reflect-Reflect-Match calibration	On-wafer VNA calibration method for mmWave probes.
SCPI	Standard Commands for Programmable Instruments	Text command set used to automate instruments.
UPH	Units Per Hour	Test throughput of a tester and handler.
eFuse	Electrically programmable fuse	Silicided poly link blown by current; stores trim, ID and repair bits.
MTP	Multiple-Time Programmable memory	Small NVM that can be rewritten a few times.
NVM	Non-Volatile Memory	Keeps data without power: eFuse, OTP, MTP, flash.
VPP	Programming supply voltage	Supply used only to program fuses or OTP.
CRC	Cyclic Redundancy Check	Checksum that detects corrupted data, e.g. trim words at boot.
RMA	Return Material Authorization	A customer return, analysed through the 8D process.
8D	Eight Disciplines	Structured problem solving: team, describe, contain, root cause, correct, verify, prevent, close.
MSA	Measurement System Analysis	Proves a measurement is precise and accurate enough (Gage R&R, bias, stability).
GRR	Gage Repeatability and Reproducibility	%GRR < 10 % of tolerance is good.
BIST	Built-In Self-Test	On-chip stimulus + measurement; result is pass/fail or a value checked against a limit.
BISM	Built-In Self-Measurement	Same on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend.
DFT	Design for Test
ATE	Automatic Test Equipment	Production tester.
ATPG	Automatic Test Pattern Generation	Scan patterns for digital logic.
IDDQ	Quiescent supply-current test	Detects leakage defects.
PMU	Parametric Measurement Unit	ATE DC source/measure channel.
Cres	Contact resistance	Probe or socket contact resistance; measured with the Kelvin or two-current method.
FIMV	Force Current, Measure Voltage	PMU mode used for open/short (diode) tests.
FVMI	Force Voltage, Measure Current	PMU mode used for leakage and power-short tests.
IIL	Input leakage current, input Low (IIH = input High)	Leakage limit per IO pin, typically \|I\| < 1 µA.
IIH	Input leakage current, input High
ESD	Electrostatic Discharge	Pad protection diodes / clamps; the diode method uses them for continuity.
VDD	Positive supply rail (VSS = ground / negative rail)
VSS	Ground / negative supply rail
DCR	DC Resistance	E.g. of an RF shunt inductor, 0.5–3 Ω.
Hi-Z	High impedance (Z)	Output driver switched off; the pin floats.
OE	Output Enable	Control that switches an output between driving and Hi-Z.
IOZ	Off-state output leakage (IOZH at VDDIO, IOZL at 0 V)	Measured on a pin in Hi-Z; typically \|I\| < 1–10 µA.
VOH	Output High voltage threshold (VOL = Output Low)	Tester comparator levels that decide 1 / Z / 0.
VOL	Output Low voltage threshold
HIGHZ	IEEE 1149.1 instruction that puts all outputs in Hi-Z
EXTEST	IEEE 1149.1 external test instruction	Boundary cells drive and sample the pins; used for interconnect and walking-Z tests.
RPCT	Reduced Pin-Count Testing	Testing through JTAG / a few pins, so more sites fit on one tester.
BICS	Built-In Current Sensor	On-chip current monitor for IDDQ per power domain.
SPC	Statistical Process Control
VNA	Vector Network Analyzer	Lab instrument for S-parameters.
AWG	Arbitrary Waveform Generator
DMM	Digital Multimeter
GPIB	General-Purpose Interface Bus	Instrument control bus (like LAN).

Safety, standards & regulation

Abbr.	Stands for	Note
PMHF	Probabilistic Metric for random Hardware Failures	ISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D.
SEooC	Safety Element out of Context	A part developed to ISO 26262 against assumed system requirements.
FMEA	Failure Mode and Effects Analysis	Qualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage.
FIT	Failures In Time	Failures per 10⁹ device-hours.
MTTF	Mean Time To Failure
RED	Radio Equipment Directive (EU 2014/53/EU)	EU conformity framework for radio transmitters, including radar.
ASIL	Automotive Safety Integrity Level	ISO 26262 risk class A–D; radar typically ASIL-B.
ISO	ISO 26262 / ISO/SAE 21434 / ISO 11452	Functional safety / cybersecurity / EMC immunity.
FTTI	Fault-Tolerant Time Interval	Time from fault to hazard; monitors must react within it.
FMEDA	Failure Modes, Effects and Diagnostic Analysis
SPFM	Single-Point Fault Metric	ISO 26262 coverage metric.
LFM	Latent Fault Metric	ISO 26262 coverage metric.
AEC	Automotive Electronics Council (AEC-Q100 / Q200)	Qualification of ICs / passives.
ETSI	European Telecommunications Standards Institute	EN 301 091 / EN 303 396 radar standards.
FCC	Federal Communications Commission	US rules, Part 95M for 76–81 GHz.
EMC	Electromagnetic Compatibility
CISPR	Comité International Spécial des Perturbations Radioélectriques	CISPR 25: vehicle-component emissions.
OOB	Out-of-Band (emission)

Digital DFT, stress & reliability

Abbr.	Stands for	Note
UHST	Unbiased Highly Accelerated Stress Test	HAST without bias, 130 °C / 85 % RH; alternative to autoclave.
PTC	Power Temperature Cycling	Temperature cycling with the device powered on and off.
EDR	Endurance and Data Retention	Qualification of non-volatile memory (AEC-Q100-005).
DPA	Destructive Physical Analysis	Opening and sectioning parts to inspect their construction and damage.
SEM	Scanning Electron Microscope	High-magnification imaging of cross-sections and surfaces.
EDX	Energy-Dispersive X-ray spectroscopy	Element analysis in the SEM: corrosion, contamination, IMC phases.
FIB	Focused Ion Beam	Precise local cutting and imaging; also used for circuit edits.
LTPD	Lot Tolerance Percent Defective	Defect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %.
PC	Preconditioning	Bake, moisture soak and reflow before environmental stress (JESD22-A113).
BLR	Board-Level Reliability	Reliability of the package soldered on a PCB (temperature cycling, drop, vibration).
SAC	Tin-Silver-Copper solder	Lead-free solder alloy (e.g. SAC305) used for balls.
PPAP	Production Part Approval Process	Automotive approval package, includes the qualification report.
DRC	Design Rule Check	Verifies layout against foundry manufacturing rules.
LVS	Layout Versus Schematic	Verifies that the layout matches the schematic netlist.
PEX	Parasitic Extraction	Extracts resistance, capacitance (and inductance) of the layout for post-layout simulation.
AMS	Analog / Mixed-Signal simulation	Simulation that combines transistor-level analog with digital models.
ECO	Engineering Change Order	Late design fix; a metal-only ECO changes only upper masks.
SCR	Silicon-Controlled Rectifier	Thyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up.
GGNMOS	Grounded-Gate NMOS	ESD clamp that works by parasitic-bipolar snapback.
SE	Scan Enable	Selects shift (SE = 1) or functional capture (SE = 0) in scan flops.
SAF	Stuck-At Fault	Node permanently 0 or 1.
TDF	Transition Delay Fault	Node slow to rise or fall; needs at-speed test.
STA	Static Timing Analysis	Finds the longest paths for timing-aware ATPG.
OCV	On-Chip Variation	Timing derates in STA that account for local (mismatch) variation across the die.
OCC	On-Chip Clock Controller	Gates exact launch/capture pulses from the PLL for at-speed test.
LOC	Launch-On-Capture	At-speed scheme; also called broadside.
LOS	Launch-On-Shift	At-speed scheme; SE must switch at speed.
EDT	Embedded Deterministic Test	Scan compression (decompressor + compactor).
LFSR	Linear-Feedback Shift Register	Pseudo-random sequence generator.
PRPG	Pseudo-Random Pattern Generator	LFSR that feeds the scan chains in LBIST.
MISR	Multiple-Input Signature Register	Compresses responses into one signature.
STUMPS	Self-Test Using MISR and Parallel Shift-register sequence generator	Standard LBIST architecture.
LBIST	Logic BIST	On-chip random-pattern scan test; used at key-on.
MBIST	Memory BIST	On-chip March-algorithm test of SRAMs.
BIRA	Built-In Redundancy Analysis	Computes which spare rows/columns repair a memory.
BISR	Built-In Self-Repair	Loads the repair from eFuse at boot.
IR	IR drop	Supply voltage drop (current × resistance), high during scan shift.
JTAG	Joint Test Action Group (IEEE 1149.1)	Boundary scan and test access port.
TAP	Test Access Port	JTAG pins TCK, TMS, TDI, TDO, TRST.
BSDL	Boundary Scan Description Language	Describes a chip's JTAG boundary-scan cells.
IJTAG	Internal JTAG (IEEE 1687)	Network for accessing on-chip instruments.
MUX	Multiplexer	Selects one of N inputs; in test, routes sub-block nodes to shared instruments.
ATB	Analog Test Bus	Chip-wide wire pair (force + sense) that test muxes connect sub-block nodes to.
TG	Transmission Gate	Parallel NMOS + PMOS switch; passes the full voltage range.
SPDT	Single-Pole Double-Throw switch	One input to one of two outputs (SP4T = one of four).
BBM	Break-Before-Make	Switching order that opens the old path before closing the new one.
ICL	Instrument Connectivity Language (PDL = Procedural Description Language)	IJTAG description files.
ECID	Electronic Chip ID	Unique per-die ID for traceability.
HVST	High-Voltage Stress Test	Short over-voltage on the core rail to activate latent oxide defects.
VLV	Very-Low-Voltage test	Test below nominal V to expose resistive defects.
Vmin	Minimum operating voltage	The pass/fail edge in a shmoo; an outlier Vmin flags a defect.
PAT	Part Average Testing (AEC-Q001)	Outlier limits at robust μ ± 6σ.
DPAT	Dynamic Part Average Testing	PAT limits recalculated per lot or wafer.
GDBN	Good Die in Bad Neighbourhood	Wafer-map screen that rejects dies in defect clusters.
NNR	Nearest-Neighbour Residual	Compares a die's parameter with its wafer neighbours.
DPPM	Defective Parts Per Million	Shipped-quality metric; automotive target ≪ 1.
FT	Final Test	Package-level production test.
SLT	System-Level Test	Functional test by booting the application.
PCM	Process Control Monitor	Test structures in the scribe lines, measured by the fab (see WAT).
WAT	Wafer Acceptance Test	Fab's electrical test of PCM structures before shipping wafers.
OSAT	Outsourced Semiconductor Assembly and Test	Company that packages and tests the dies.
QA	Quality Assurance	Sample-based outgoing inspection and audits.
Cp	Process capability (Cp)	(USL − LSL) / 6σ: spec width vs process spread.
Cpk	Process capability index	min(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67.
USL	Upper Spec Limit (LSL = Lower Spec Limit)	Design limits; outside them the part is out of spec.
LSL	Lower Spec Limit
UCL	Upper Control Limit (LCL = Lower Control Limit)	Process limits from history, usually mean ± 3σ.
LCL	Lower Control Limit
OCAP	Out-of-Control Action Plan	Documented steps when an SPC rule fires.
MRB	Material Review Board	Decides what happens to held material: release, rework, scrap or deviation.
MIM	Metal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal)	Precision on-chip capacitors.
MOM	Metal-Oxide-Metal (finger) capacitor
BSIM	Berkeley Short-channel IGFET Model	Industry-standard compact transistor model family used in design kits.
Vt	Threshold voltage	Gate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD.
Idsat	Saturation drain current	Id at Vgs = Vds = VDD, per µm of width; transistor strength.
Ioff	Off-state leakage current	Id at Vgs = 0, Vds = VDD.
DIBL	Drain-Induced Barrier Lowering	Vt drop per volt of Vds in short-channel devices.
SS	Subthreshold swing (also SS = slow-slow process corner)	mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature.
TT	Typical-typical process corner	FF = fast-fast; FS / SF = skewed NMOS / PMOS corners.
FF	Fast-fast process corner
gm	Transconductance	∂Id/∂Vgs; the transistor's gain.
gds	Output conductance	∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds).
Cox	Gate-oxide capacitance per area	εox / Tox.
Tox	Gate-oxide thickness	Measured with C-V structures in WAT.
fT	Transit (unity current-gain) frequency	≈ gm / 2π(Cgs + Cgd).
fmax	Maximum oscillation (unity power-gain) frequency	Needs ≈ 3–4× the operating frequency for useful gain.
Vbd	Gate-oxide breakdown voltage	Voltage where oxide current jumps past compliance in a V-ramp test.
BV	Breakdown Voltage	BVdss = drain-source (gate off), BVj = junction.
BVdss	Drain-source breakdown voltage	Transistor off-state breakdown; limits PA drain swing.
BVj	Junction breakdown voltage	Reverse breakdown of N+/P-well or P+/N-well diodes.
TLP	Transmission-Line Pulse	ESD device characterisation with short, high-current pulses.
QBD	Charge to breakdown	Total charge an oxide passes before breaking down (reliability).
IMD	Inter-Metal Dielectric	Insulator between metal lines/layers; tested with comb structures.
CMP	Chemical-Mechanical Planarization	Polishing step that flattens each layer; source of centre, edge and ring signatures.
OPC	Optical Proximity Correction	Mask shape corrections; weak spots (hotspots) can fail per reticle shot.
EBR	Edge Bead Removal	Removes resist build-up at the wafer edge.
D0	Defect density	Random defects per unit area; baseline yield Y ≈ e^(−D0·A).
HTOL	High-Temperature Operating Life	≈ 1000 h biased at max temperature (AEC-Q100).
ELFR	Early Life Failure Rate	Short high-temperature operation of a large sample.
TC	Temperature Cycling	Package and interconnect fatigue test.
THB	Temperature-Humidity-Bias	85 °C / 85% RH with bias.
HAST	Highly Accelerated Stress Test	130 °C / 85% RH with bias.
RH	Relative Humidity
HTSL	High-Temperature Storage Life	Unbiased bake.
HBM	Human-Body Model (ESD)
CDM	Charged-Device Model (ESD)
LU	Latch-Up	JESD78 test.
EM	Electromigration	Metal wear-out under current (wafer-level reliability).
TDDB	Time-Dependent Dielectric Breakdown	Gate-oxide wear-out.
HCI	Hot-Carrier Injection	Transistor degradation mechanism.
NBTI	Negative-Bias Temperature Instability	PMOS threshold drift.

PCB, package & materials

Abbr.	Stands for	Note
TCB	Thermo-Compression Bonding	Flip-chip attach with heat and force per die; fine pitch, low warpage.
MUF	Molded Underfill	Mold compound that also fills the gap under a flip-chip die.
CSAM	C-mode Scanning Acoustic Microscopy	Ultrasound imaging of voids and delamination inside packages.
AOI	Automated Optical Inspection	Camera inspection of RDL, bumps and balls in the assembly line.
KGD	Known-Good Die	Die that passed wafer sort and is released for assembly.
WLP	Wafer-Level Package	Package built on the whole wafer (fan-in) or a reconstituted wafer (fan-out).
PCB	Printed Circuit Board
RDL	Redistribution Layer	Thin-film Cu wiring that routes die pads to balls (fan-out) or bumps.
UBM	Under-Bump Metallisation	Metal stack between die/RDL pad and the solder.
FOWLP	Fan-Out Wafer-Level Package	Die embedded in mold with RDL fanning out to balls; eWLB is one type.
CSP	Chip-Scale Package	Package only slightly larger than the die (FC-CSP = flip-chip CSP).
AiP	Antenna-in-Package	Antennas built into package layers.
IMC	Intermetallic Compound	Layer formed between solder and UBM/pad; grows with time and temperature.
CTE	Coefficient of Thermal Expansion	Mismatch between materials drives solder and bump fatigue.
MSL	Moisture Sensitivity Level	J-STD-020 rating: how long a package may sit out of dry pack before reflow.
ELK	Extreme Low-k dielectric	Fragile back-end dielectric in advanced nodes; cracks under bump stress.
NSMD	Non-Solder-Mask-Defined pad	PCB pad style that improves solder-joint fatigue life.
Dk	Dielectric constant	Sets line impedance and antenna tuning; shifts with moisture.
Df	Dissipation factor	Dielectric loss; key for RF loss at 77 GHz.
C-SAM	C-mode Scanning Acoustic Microscopy	Non-destructive imaging of delamination and voids.
PBO	Polybenzoxazole	Polymer dielectric used in RDL (like polyimide).
EOS	Electrical Overstress	Damage from overvoltage or overcurrent beyond ESD events.
BGA	Ball Grid Array	FC-BGA = flip-chip BGA.
eWLB	embedded Wafer-Level Ball-grid-array	Fan-out package with low RF loss.
AoP	Antenna-on-Package
LoP	Launch-on-Package	RF launched from package into waveguide / antenna.
GCPW	Grounded Coplanar Waveguide	PCB transmission line at the ball launch.
SIW	Substrate-Integrated Waveguide	Waveguide formed with via fences in the PCB.
FR4	Flame-Retardant epoxy-glass laminate	Standard low-cost PCB material.
ENEPIG	Electroless Nickel, Electroless Palladium, Immersion Gold	PCB surface finish.
ImAg	Immersion Silver	PCB surface finish.
HASL	Hot-Air Solder Leveling	Surface finish; too rough/uneven for 77 GHz.
PBT	Polybutylene terephthalate (PC = polycarbonate)	Radome plastics.
HFSS	High-Frequency Structure Simulator (Ansys)	3D EM simulator (CST = Dassault's equivalent).