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77 GHz radar · applications

ADAS applications

The driving functions a 77 GHz radar serves, with animated scenarios (ACC, pedestrian AEB, blind-spot and lane-change assist, rear cross-traffic), the sensor classes, how each application turns into chip requirements, the rules that drive adoption and the market trends.

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ADAS applications: what the radar is for

System

Everything on the other pages exists to serve a handful of driving functions. This page shows what those functions ask of the radar, and how that reaches down to the chip: why a front radar needs Tx power and phase noise, why a corner radar needs a wide field of view and 4 GHz of bandwidth, and why every one of them needs safety monitors.

Animated scenarios

Pick a scenario. The scene shows the traffic from above with each active radar's field of view (shaded) and its transmitted chirps (expanding rings, illustrative). The panel on the right is what the radar actually reports: a point cloud of detections with range, radial velocity and angle. The status line is the driving function's decision.

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About the animation. It is drawn live in the page (no video file), follows the light/dark theme, starts paused if your system asks for reduced motion, and stops while it is scrolled out of view. Distances are simplified and the side view is not to scale. "Save as video" records one loop of the current scenario as a WebM file (Chrome, Edge, Firefox).

Driving functions and what they need from the radar

FunctionWhat it doesSensorRange · FoVWhat the radar must deliverChip features that matter
ACC / stop-and-goHolds a set speed and a time gap to the vehicle aheadFront LRR (+ MRR)≈ 200–300 m · ±10–20°Range and speed of the lead car; lane assignment from angleTx power, noise figure, phase noise, angle calibration
AEB car-to-car / FCWWarns, then brakes automatically before a collisionFront LRR/MRR + camera≈ 80–160 m · ±30–60°Time-to-collision from range and closing speed; very few false alarmsFrame update ≈ 20–50 ms, detection stability, safety monitors (ASIL B)
AEB VRU (pedestrian, cyclist)Brakes for pedestrians and cyclists, crossing or turningFront MRR + camera≈ 50–80 m · ±50–75°Low-RCS targets (−10…0 dBsm) next to cars and clutter; micro-Doppler of walkingRange resolution, dynamic range (HPF, ADC, saturation detectors), angle resolution
BSDWarns of a vehicle in the blind spotRear corner SRR ×2≈ 30–80 m · ±75°Presence in a zone beside and behind the carWide-FoV antennas, near-range performance, leakage handling
LCAWarns of a fast vehicle approaching in the next laneRear corner SRR/MRR≈ 70–100 m rearwardsClosing speed and TTC from behindVelocity measurement, range
RCTA / RCTBWarns (and brakes) when reversing into cross trafficRear corner SRR ×2≈ 30–50 m · ±75–90°Crossing targets behind the car, partly hidden by parked carsSensitivity at large angles, fast reaction, clutter handling
FCTAFront cross-traffic alert at junctions and drivewaysFront corner SRR ×2≈ 30–60 m · ±75°Crossing targets at large anglesAs RCTA
DOWWarns an occupant before opening a door into a cyclistRear corner SRR≈ 30 mApproaching targets beside the parked carLow-power monitoring mode
Highway pilot (L2+ / L3)Hands-off or eyes-off driving on the highwayFront 4D imaging + 4 corners≈ 250–300 m · ±60° az, elevationSeparate stationary objects (debris, bridges) in elevation; fine angular resolutionMany channels (12×16 virtual and up), cascaded or high-channel chips, high data rate
Parking and low-speed manoeuvringObstacles around the car at walking speedCorner SRR (with or instead of ultrasonic)≈ 0.2–30 m · ±75°Very short range, fine resolutionFull 4 GHz bandwidth (77–81 GHz), near-field performance

Radar sensor classes

Sensor classBand / bandwidthRangeFoV (azimuth)Range resolutionTx × Rx (virtual)Typical chirp
LRR (front long range)76–77 GHz · ≈ 0.5–1 GHz≈ 200–300 m±10–20° (plus a wider near mode)≈ 15–30 cm3 × 4 (12)Slow slope, long ramp, 256–512 samples
MRR (front or rear mid range)76–81 GHz · ≈ 1–2 GHz≈ 80–160 m±40–60°≈ 7.5–15 cm3 × 4 (12)Medium slope
SRR (corner)77–81 GHz · up to 4 GHz≈ 30–80 m±75–90°≈ 3.75–7.5 cm2 × 4 or 3 × 4Steep, short chirps
4D imaging76–81 GHz · ≈ 1–2 GHz≈ 250–300 m±60° (plus ±15° elevation)≈ 7.5–15 cm12 × 16 (192) and moreSeveral interleaved profiles

A typical modern car has one front radar and four corner radars ("5R"); premium and L2+/L3 cars replace the front radar with a 4D imaging radar. Today one RFCMOS chip family often covers all classes; the antenna, the chirp profile and the software differ.

From application to chip requirements

Range resolution ΔR = c / (2·B) B = 1 GHz → 15 cm, 4 GHz → 3.75 cm Maximum range (IF) R_max = f_IF,max · c / (2·S) S = chirp slope Maximum velocity v_max = λ / (4·T_c) T_c = chirp period, λ ≈ 3.9 mm Velocity resolution Δv = λ / (2·N_chirps·T_c) Angle resolution Δθ ≈ 2 / N_virtual (rad, at boresight) Time to collision TTC = R / v_closing
What the application needsRadar parameterSet by (chip and page)
See a car at 200 m or moreMaximum range, SNRTx power, NF, antenna gain, phase noise · link budget, RF front end
Separate a pedestrian from a parked carRange resolution c / 2BChirp bandwidth and linearity · synthesizer
Measure fast closing speedsv_max = λ / (4·T_c)Chirp period, ramp reset time · synthesizer, DSP
Separate two cars side by sideAngle resolution ≈ 2 / N_virtual radNumber of channels, phase calibration · BIST, phase rotator
See weak targets next to strong onesDynamic rangeHPF, PGA/AGC, ADC SNR, saturation detectors · IF & ADC
React within one frameFrame time, latencyDSP throughput, data interface · DSP
Work among many other radarsInterference robustnessChirp randomisation, burst repair · interference
Fail safelyDiagnostic coverage within the FTTIMonitors, BIST, key-on tests · functional safety

Regulations and ratings that drive adoption

  • EU General Safety Regulation (EU) 2019/2144: makes AEB, emergency lane keeping and other assistance functions mandatory for new vehicle types from July 2022 and for all new registrations from July 2024, with pedestrian and cyclist AEB in later phases.
  • USA, FMVSS No. 127 (NHTSA final rule, 2024): requires AEB, including pedestrian AEB, on new light vehicles, with compliance from September 2029.
  • NCAP ratings (Euro NCAP, C-NCAP, IIHS and others) score AEB car-to-car, AEB VRU, junction, blind-spot and lane-change cases; top scores in practice need a front radar plus corner radars together with a camera.
  • Rules and protocols change often; check the current editions. The radio rules themselves are on the regulations page.
  • More radars per car: from one front radar to five or more, driven by NCAP corner and junction scenarios.
  • 4D imaging radar for L2+ and L3: elevation measurement and many more channels, by cascading chips or with high-channel single chips.
  • Central processing: "satellite" radar heads send raw or range-FFT data over Ethernet or CSI-2 to a central computer instead of a full object list (data interfaces).
  • Antenna in package and launch-on-package remove the RF printed-circuit launch and simplify the module (package page).
  • Interference grows with the number of radars on the road, so mitigation becomes a requirement (interference).
  • In-cabin radar at 60 GHz for child-presence detection and occupant monitoring uses the same FMCW principles in a different band.
Values are typical for 77 GHz automotive radar SoCs and meant for planning; check your process, product and customer requirements.
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Glossary of abbreviations

Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.

Radar system & ADAS

Abbr.Stands forNote
FCWForward Collision WarningWarns of an imminent frontal collision; stage before AEB.
FCTAFront Cross-Traffic AlertFront corner-radar function at junctions and driveways.
RCTBRear Cross-Traffic BrakingBrakes automatically when RCTA detects cross traffic while reversing.
DOWDoor-Opening WarningWarns before a door is opened into an approaching cyclist or car.
VRUVulnerable Road UserPedestrians, cyclists and motorcyclists.
TTCTime To CollisionRange divided by closing speed; triggers warnings and braking.
LRRLong-Range RadarFront radar, ≈ 200–300 m, narrow field of view.
MRRMid-Range Radar≈ 80–160 m, ±40–60° field of view.
SRRShort-Range RadarCorner radar, ≈ 30–80 m, ±75–90° field of view.
NCAPNew Car Assessment ProgrammeConsumer safety ratings (Euro NCAP, C-NCAP, IIHS …).
GSRGeneral Safety Regulation (EU) 2019/2144Makes AEB and other assistance functions mandatory in the EU.
CPDChild Presence DetectionIn-cabin sensing (often 60 GHz radar) that detects a child left in the car.
ACCAdaptive Cruise ControlKeeps distance to the car ahead; uses long-range front radar.
ADASAdvanced Driver-Assistance SystemsThe vehicle functions the radar serves.
AEBAutonomous Emergency BrakingBrakes automatically when a collision is imminent.
BSDBlind-Spot DetectionCorner-radar function.
LCALane-Change AssistCorner-radar function that warns of fast approaching vehicles.
RCTARear Cross-Traffic AlertRear corner-radar function when reversing.
L2SAE automation Level 2 (L3 = Level 3)Partial (L2) and conditional (L3) driving automation.
FMCWFrequency-Modulated Continuous WaveA linear chirp; range comes from the beat frequency f_b = S·2R/c.
FoVField of ViewAngular coverage in azimuth and elevation.
RCSRadar Cross SectionTarget reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0).
dBsmDecibels relative to 1 m²Unit of RCS.
EIRPEffective Isotropic Radiated PowerTx power + antenna gain; limited by regulations.
MIMOMultiple-Input Multiple-OutputN_tx × N_rx channels form a larger virtual array.
TDMTime-Division MultiplexingOne Tx per chirp; v_max falls by a factor of N_tx.
BPMBinary Phase Modulation0/180° codes across chirps separate the Tx signals.
DDMADoppler-Division Multiple AccessEach Tx gets a slow-time phase ramp and separates in Doppler.
DoADirection of ArrivalAngle estimation over the virtual array.
DBFDigital BeamformingFFT or matched steering over array channels.
CFARConstant False Alarm RateAdaptive detection threshold (CA = cell-averaging, OS = ordered-statistic).
FFTFast Fourier TransformRange, Doppler and angle FFTs build the radar cube.
SNRSignal-to-Noise Ratio
MUSICMUltiple SIgnal ClassificationSubspace super-resolution DoA algorithm.
ESPRITEstimation of Signal Parameters via Rotational Invariance TechniquesSuper-resolution DoA algorithm.
IAAIterative Adaptive ApproachSuper-resolution spectral / DoA estimator.
DBSCANDensity-Based Spatial Clustering of Applications with NoiseGroups detections into objects.
EKFExtended Kalman FilterNonlinear tracking filter.
UKFUnscented Kalman FilterNonlinear tracking filter using sigma points.
IMMInteracting Multiple ModelTracker that mixes several motion models.
HWAHardware AcceleratorOn-chip FFT / radar processing engine.
RTSRadar Target SimulatorEcho generator for HIL and EOL testing.
HILHardware-in-the-LoopTesting the real sensor against simulated scenarios.
EOLEnd-of-LineFinal production test of a module or vehicle.

RF & analog front end

Abbr.Stands forNote
HPBWHalf-Power BeamwidthAngle between the −3 dB points of an antenna or array beam.
PDNPower Delivery NetworkRegulators, planes, decoupling and package paths that supply the chip.
PIPower IntegrityKeeping supply voltage within limits under load steps and noise.
EMIElectromagnetic InterferenceUnwanted emission or pick-up of electromagnetic energy.
BCIBulk Current InjectionImmunity test (ISO 11452-4) that injects RF current into a cable harness.
TIMThermal Interface MaterialGap pad or paste between board or package and the heat sink.
RFRadio FrequencyHere the 76–81 GHz signal.
LOLocal OscillatorThe chirp signal that drives the Tx and the Rx mixers.
IFIntermediate FrequencyThe beat / baseband signal after the mixer, DC–20 MHz.
PAPower AmplifierTx output stage, 12–14 dBm.
LNALow-Noise AmplifierFirst Rx stage; sets most of the NF.
NFNoise FigureNoise the receiver adds, in dB.
VGAVariable-Gain AmplifierProgrammable-gain stage (IF), or signed VGAs in the phase rotator.
TIATransimpedance AmplifierCurrent-to-voltage stage after a passive mixer.
HPFHigh-Pass FilterIn IF: removes leakage and DC, and equalises R⁻⁴.
LPFLow-Pass Filter
AAFAnti-Aliasing FilterLow-pass filter in front of the ADC.
PPFPolyphase FilterRC-CR network that generates I/Q.
I/QIn-phase / QuadratureTwo copies of a signal 90° apart.
IRRImage Rejection RatioHow well an I/Q path suppresses the mirror frequency.
SSBSingle SidebandA frequency shift in one direction only, e.g. the loopback offset.
BPSKBinary Phase-Shift Keying0/180° switching; produces ±f_m sidebands.
VMVector ModulatorI/Q-weighted phase rotator.
RTPSReflection-Type Phase ShifterHybrid coupler terminated by tunable loads.
P1dB1 dB compression pointInput (or output) level where gain drops by 1 dB.
IIP3Input third-order intercept pointLinearity figure; cascades with the gain before each stage.
PAEPower-Added Efficiency(P_out − P_in) / P_DC of a PA.
PsatSaturated output powerMaximum output power of a PA.
DSBDouble SidebandNoise figure counting both sidebands (typical for zero-IF mixers).
PGAProgrammable-Gain AmplifierIF VGA with digitally set gain steps.
AGCAutomatic Gain ControlLoop that sets the VGA gain from the signal level.
HD22nd-order Harmonic Distortion (HD3 = 3rd)Harmonics show up as ghost targets at 2×/3× range.
AM/PMAmplitude-to-phase conversionPhase change caused by amplitude or supply changes.
RLReturn LossMatch quality, in dB.
CplCoupler (directional coupler)Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback.
PDPower DetectorDiode or square-law RF-to-DC converter.
APCAutomatic Power ControlClosed loop from the power detector to the VGA/PA gain code.
DPDDigital PredistortionWideband PA linearisation used in comms; radar uses static gain/phase LUTs instead.
VSWRVoltage Standing-Wave RatioMismatch at the antenna/load; changes the delivered power.
CWContinuous WaveAn unmodulated single-frequency tone.
ENRExcess Noise RatioCalibrated output level of a noise source.
SiGeSilicon-Germanium (BiCMOS)Bipolar-plus-CMOS process used for earlier radar chips.
CMOSComplementary Metal-Oxide-SemiconductorRFCMOS = CMOS process with RF / mmWave capability.
RFCMOSRF-capable CMOSToday's single-chip radar process (e.g. 45/40/28/22 nm).
NMOSN-channel MOS transistor (PMOS = P-channel)
PTATProportional To Absolute TemperatureVoltage or current used by temperature sensors.
BGBandgap referenceTemperature-stable voltage reference (BG1/BG2 = two independent ones).
PVTProcess, Voltage, TemperatureVariation corners a design must cover.

LO, clock & synthesis

Abbr.Stands forNote
PLLPhase-Locked LoopLocks the VCO to the crystal and generates the ramp.
ADPLLAll-Digital PLLPLL with a TDC and a digital loop filter.
VCOVoltage-Controlled Oscillator≈ 19–20.25 GHz, multiplied ×4 to 77 GHz.
PFDPhase-Frequency DetectorCompares the divided VCO with the reference.
CPCharge Pump; also Chip ProbeIn a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test.
TDCTime-to-Digital ConverterDigital phase detector of an ADPLL.
XTALCrystal (reference oscillator)40/50 MHz reference for PLL, ADC and digital.
DDSDirect Digital SynthesizerDigitally generated tone (IF test tone).
KvcoVCO gainTuning sensitivity in MHz/V; varies per band.
AFCAutomatic Frequency Calibration (band calibration)Picks the VCO capacitor-bank band before the PLL closes.
MMDMulti-Modulus DividerProgrammable divider in the PLL feedback, dithered by the ΣΔ modulator.
CMLCurrent-Mode LogicFast differential logic used for the first divider (prescaler) stages at 20 GHz.

Data conversion & digital

Abbr.Stands forNote
SNMStatic Noise MarginNoise an SRAM cell tolerates before flipping; read SNM is the critical one.
SEUSingle-Event UpsetBit flip caused by a particle strike (soft error).
SERSoft-Error RateRate of radiation-induced bit flips, in FIT per Mbit.
MBUMulti-Bit UpsetOne particle flips several neighbouring cells.
RDFRandom Dopant FluctuationRandom number of dopant atoms in a small channel; main cause of Vth mismatch.
LERLine-Edge RoughnessRough gate edges that add Vth variation in small devices.
NPSFNeighbourhood Pattern-Sensitive FaultMemory cell fails only for certain data in its neighbours.
SEC-DEDSingle-Error Correction, Double-Error DetectionECC code used on memory words (e.g. 64 + 8 bits).
ROMRead-Only MemoryMask-programmed memory for boot code and tables.
DRFData-Retention FaultMemory cell loses its value after a pause.
WLWord LineRow select line of a memory array.
BLBit LineColumn data line of a memory array (BL and its complement BLB).
OSROversampling Ratiofs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR.
NTFNoise Transfer FunctionHow a ΣΔ loop shapes quantisation noise out of the signal band.
SNDRSignal-to-Noise-and-Distortion RatioENOB = (SNDR − 1.76) / 6.02.
GBWGain-Bandwidth productOp-amp figure of merit; sets filter and PGA accuracy at IF.
CMRRCommon-Mode Rejection RatioHow well a differential circuit rejects signals common to both inputs.
CSI-2MIPI Camera Serial Interface 2High-speed serial link used for raw radar data.
TSNTime-Sensitive NetworkingDeterministic automotive Ethernet (IEEE 802.1).
ADCAnalog-to-Digital ConverterMain Rx ADCs (ΣΔ) and the aux SAR ADC.
DACDigital-to-Analog ConverterRotator I/Q weights, bias, trim, test-tone generation.
SARSuccessive-Approximation Register ADCSlow, precise ADC used for monitoring.
CTContinuous-Time (CT-ΣΔ)Sigma-delta ADC with a continuous-time loop filter.
ENOBEffective Number of Bits
SFDRSpurious-Free Dynamic RangeTone relative to the largest spur.
THDTotal Harmonic Distortion
DRDynamic Range
INLIntegral NonlinearityDeviation from the ideal transfer line.
DNLDifferential NonlinearityDeviation of each step from 1 LSB.
LSBLeast Significant Bit (MSB = most significant)
DFEDigital Front EndDecimation, DC and I/Q correction, interference handling.
CICCascaded Integrator-CombMultiplier-free decimation filter.
FIRFinite Impulse Response filter
DSPDigital Signal Processor
MCUMicrocontroller Unit
CPUCentral Processing UnitE.g. the RF control CPU that runs chirps and monitors.
SoCSystem-on-Chip
ECUElectronic Control UnitVehicle computer that receives radar data.
SRAMStatic RAM (RAM = random-access memory)
ECCError-Correcting CodeMemory protection for functional safety.
DMADirect Memory Access
LUTLook-Up TableE.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature.
FWFirmware (SW = software)
OTPOne-Time Programmable memoryHolds trims and IDs, like eFuse.
SPISerial Peripheral InterfaceConfiguration / test bus from host or ATE.
CANController Area Network (CAN-FD = Flexible Data-rate)Vehicle bus for object lists.
ETHEthernet (100/1000BASE-T1)Automotive single-pair Ethernet.
CSICamera Serial Interface (MIPI CSI-2)Streams raw radar data to a central SoC.
LVDSLow-Voltage Differential SignalingRaw-data debug / streaming interface.
GPIOGeneral-Purpose Input/Output
IOInput/Output

Power

Abbr.Stands forNote
LDOLow-Dropout regulatorLinear regulator; one per noise-sensitive domain.
PMICPower-Management ICExternal bucks, supervisors and watchdog.
PSRRPower-Supply Rejection RatioHow much supply ripple an LDO (or circuit) blocks.
UVUnder-Voltage (OV = Over-Voltage)Supply monitors, a safety mechanism.
OVOver-VoltageRail above its window; OV monitor protects gate oxides.
PORPower-On ResetHolds the chip in reset until all rails are valid.
BORBrown-Out ResetResets when a supply sags during operation.
ESREquivalent Series ResistanceOf the LDO output capacitor; its zero affects loop stability.
OCPOver-Current ProtectionCurrent limit on a regulator output.
IqQuiescent currentCurrent a regulator draws for itself with no load.
DLDODigital LDOSwitched pass-device array regulated by a comparator loop.
GNDGround

Test & production

Abbr.Stands forNote
EVBEvaluation BoardBoard that carries the chip on the bench with supplies, clock, interfaces and RF transitions.
SMUSource-Measure UnitPrecision instrument that forces voltage or current and measures the other.
OTAOver The AirMeasurement through antennas in a chamber instead of a cable or waveguide.
GSGGround-Signal-Ground probeRF wafer probe with a signal tip between two ground tips.
LRRMLine-Reflect-Reflect-Match calibrationOn-wafer VNA calibration method for mmWave probes.
SCPIStandard Commands for Programmable InstrumentsText command set used to automate instruments.
UPHUnits Per HourTest throughput of a tester and handler.
eFuseElectrically programmable fuseSilicided poly link blown by current; stores trim, ID and repair bits.
MTPMultiple-Time Programmable memorySmall NVM that can be rewritten a few times.
NVMNon-Volatile MemoryKeeps data without power: eFuse, OTP, MTP, flash.
VPPProgramming supply voltageSupply used only to program fuses or OTP.
CRCCyclic Redundancy CheckChecksum that detects corrupted data, e.g. trim words at boot.
RMAReturn Material AuthorizationA customer return, analysed through the 8D process.
8DEight DisciplinesStructured problem solving: team, describe, contain, root cause, correct, verify, prevent, close.
MSAMeasurement System AnalysisProves a measurement is precise and accurate enough (Gage R&R, bias, stability).
GRRGage Repeatability and Reproducibility%GRR < 10 % of tolerance is good.
BISTBuilt-In Self-TestOn-chip stimulus + measurement; result is pass/fail or a value checked against a limit.
BISMBuilt-In Self-MeasurementSame on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend.
DFTDesign for Test
ATEAutomatic Test EquipmentProduction tester.
ATPGAutomatic Test Pattern GenerationScan patterns for digital logic.
IDDQQuiescent supply-current testDetects leakage defects.
PMUParametric Measurement UnitATE DC source/measure channel.
CresContact resistanceProbe or socket contact resistance; measured with the Kelvin or two-current method.
FIMVForce Current, Measure VoltagePMU mode used for open/short (diode) tests.
FVMIForce Voltage, Measure CurrentPMU mode used for leakage and power-short tests.
IILInput leakage current, input Low (IIH = input High)Leakage limit per IO pin, typically |I| < 1 µA.
IIHInput leakage current, input High
ESDElectrostatic DischargePad protection diodes / clamps; the diode method uses them for continuity.
VDDPositive supply rail (VSS = ground / negative rail)
VSSGround / negative supply rail
DCRDC ResistanceE.g. of an RF shunt inductor, 0.5–3 Ω.
Hi-ZHigh impedance (Z)Output driver switched off; the pin floats.
OEOutput EnableControl that switches an output between driving and Hi-Z.
IOZOff-state output leakage (IOZH at VDDIO, IOZL at 0 V)Measured on a pin in Hi-Z; typically |I| < 1–10 µA.
VOHOutput High voltage threshold (VOL = Output Low)Tester comparator levels that decide 1 / Z / 0.
VOLOutput Low voltage threshold
HIGHZIEEE 1149.1 instruction that puts all outputs in Hi-Z
EXTESTIEEE 1149.1 external test instructionBoundary cells drive and sample the pins; used for interconnect and walking-Z tests.
RPCTReduced Pin-Count TestingTesting through JTAG / a few pins, so more sites fit on one tester.
BICSBuilt-In Current SensorOn-chip current monitor for IDDQ per power domain.
SPCStatistical Process Control
VNAVector Network AnalyzerLab instrument for S-parameters.
AWGArbitrary Waveform Generator
DMMDigital Multimeter
GPIBGeneral-Purpose Interface BusInstrument control bus (like LAN).

Safety, standards & regulation

Abbr.Stands forNote
PMHFProbabilistic Metric for random Hardware FailuresISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D.
SEooCSafety Element out of ContextA part developed to ISO 26262 against assumed system requirements.
FMEAFailure Mode and Effects AnalysisQualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage.
FITFailures In TimeFailures per 10⁹ device-hours.
MTTFMean Time To Failure
REDRadio Equipment Directive (EU 2014/53/EU)EU conformity framework for radio transmitters, including radar.
ASILAutomotive Safety Integrity LevelISO 26262 risk class A–D; radar typically ASIL-B.
ISOISO 26262 / ISO/SAE 21434 / ISO 11452Functional safety / cybersecurity / EMC immunity.
FTTIFault-Tolerant Time IntervalTime from fault to hazard; monitors must react within it.
FMEDAFailure Modes, Effects and Diagnostic Analysis
SPFMSingle-Point Fault MetricISO 26262 coverage metric.
LFMLatent Fault MetricISO 26262 coverage metric.
AECAutomotive Electronics Council (AEC-Q100 / Q200)Qualification of ICs / passives.
ETSIEuropean Telecommunications Standards InstituteEN 301 091 / EN 303 396 radar standards.
FCCFederal Communications CommissionUS rules, Part 95M for 76–81 GHz.
EMCElectromagnetic Compatibility
CISPRComité International Spécial des Perturbations RadioélectriquesCISPR 25: vehicle-component emissions.
OOBOut-of-Band (emission)

Digital DFT, stress & reliability

Abbr.Stands forNote
UHSTUnbiased Highly Accelerated Stress TestHAST without bias, 130 °C / 85 % RH; alternative to autoclave.
PTCPower Temperature CyclingTemperature cycling with the device powered on and off.
EDREndurance and Data RetentionQualification of non-volatile memory (AEC-Q100-005).
DPADestructive Physical AnalysisOpening and sectioning parts to inspect their construction and damage.
SEMScanning Electron MicroscopeHigh-magnification imaging of cross-sections and surfaces.
EDXEnergy-Dispersive X-ray spectroscopyElement analysis in the SEM: corrosion, contamination, IMC phases.
FIBFocused Ion BeamPrecise local cutting and imaging; also used for circuit edits.
LTPDLot Tolerance Percent DefectiveDefect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %.
PCPreconditioningBake, moisture soak and reflow before environmental stress (JESD22-A113).
BLRBoard-Level ReliabilityReliability of the package soldered on a PCB (temperature cycling, drop, vibration).
SACTin-Silver-Copper solderLead-free solder alloy (e.g. SAC305) used for balls.
PPAPProduction Part Approval ProcessAutomotive approval package, includes the qualification report.
DRCDesign Rule CheckVerifies layout against foundry manufacturing rules.
LVSLayout Versus SchematicVerifies that the layout matches the schematic netlist.
PEXParasitic ExtractionExtracts resistance, capacitance (and inductance) of the layout for post-layout simulation.
AMSAnalog / Mixed-Signal simulationSimulation that combines transistor-level analog with digital models.
ECOEngineering Change OrderLate design fix; a metal-only ECO changes only upper masks.
SCRSilicon-Controlled RectifierThyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up.
GGNMOSGrounded-Gate NMOSESD clamp that works by parasitic-bipolar snapback.
SEScan EnableSelects shift (SE = 1) or functional capture (SE = 0) in scan flops.
SAFStuck-At FaultNode permanently 0 or 1.
TDFTransition Delay FaultNode slow to rise or fall; needs at-speed test.
STAStatic Timing AnalysisFinds the longest paths for timing-aware ATPG.
OCVOn-Chip VariationTiming derates in STA that account for local (mismatch) variation across the die.
OCCOn-Chip Clock ControllerGates exact launch/capture pulses from the PLL for at-speed test.
LOCLaunch-On-CaptureAt-speed scheme; also called broadside.
LOSLaunch-On-ShiftAt-speed scheme; SE must switch at speed.
EDTEmbedded Deterministic TestScan compression (decompressor + compactor).
LFSRLinear-Feedback Shift RegisterPseudo-random sequence generator.
PRPGPseudo-Random Pattern GeneratorLFSR that feeds the scan chains in LBIST.
MISRMultiple-Input Signature RegisterCompresses responses into one signature.
STUMPSSelf-Test Using MISR and Parallel Shift-register sequence generatorStandard LBIST architecture.
LBISTLogic BISTOn-chip random-pattern scan test; used at key-on.
MBISTMemory BISTOn-chip March-algorithm test of SRAMs.
BIRABuilt-In Redundancy AnalysisComputes which spare rows/columns repair a memory.
BISRBuilt-In Self-RepairLoads the repair from eFuse at boot.
IRIR dropSupply voltage drop (current × resistance), high during scan shift.
JTAGJoint Test Action Group (IEEE 1149.1)Boundary scan and test access port.
TAPTest Access PortJTAG pins TCK, TMS, TDI, TDO, TRST.
BSDLBoundary Scan Description LanguageDescribes a chip's JTAG boundary-scan cells.
IJTAGInternal JTAG (IEEE 1687)Network for accessing on-chip instruments.
MUXMultiplexerSelects one of N inputs; in test, routes sub-block nodes to shared instruments.
ATBAnalog Test BusChip-wide wire pair (force + sense) that test muxes connect sub-block nodes to.
TGTransmission GateParallel NMOS + PMOS switch; passes the full voltage range.
SPDTSingle-Pole Double-Throw switchOne input to one of two outputs (SP4T = one of four).
BBMBreak-Before-MakeSwitching order that opens the old path before closing the new one.
ICLInstrument Connectivity Language (PDL = Procedural Description Language)IJTAG description files.
ECIDElectronic Chip IDUnique per-die ID for traceability.
HVSTHigh-Voltage Stress TestShort over-voltage on the core rail to activate latent oxide defects.
VLVVery-Low-Voltage testTest below nominal V to expose resistive defects.
VminMinimum operating voltageThe pass/fail edge in a shmoo; an outlier Vmin flags a defect.
PATPart Average Testing (AEC-Q001)Outlier limits at robust μ ± 6σ.
DPATDynamic Part Average TestingPAT limits recalculated per lot or wafer.
GDBNGood Die in Bad NeighbourhoodWafer-map screen that rejects dies in defect clusters.
NNRNearest-Neighbour ResidualCompares a die's parameter with its wafer neighbours.
DPPMDefective Parts Per MillionShipped-quality metric; automotive target ≪ 1.
FTFinal TestPackage-level production test.
SLTSystem-Level TestFunctional test by booting the application.
PCMProcess Control MonitorTest structures in the scribe lines, measured by the fab (see WAT).
WATWafer Acceptance TestFab's electrical test of PCM structures before shipping wafers.
OSATOutsourced Semiconductor Assembly and TestCompany that packages and tests the dies.
QAQuality AssuranceSample-based outgoing inspection and audits.
CpProcess capability (Cp)(USL − LSL) / 6σ: spec width vs process spread.
CpkProcess capability indexmin(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67.
USLUpper Spec Limit (LSL = Lower Spec Limit)Design limits; outside them the part is out of spec.
LSLLower Spec Limit
UCLUpper Control Limit (LCL = Lower Control Limit)Process limits from history, usually mean ± 3σ.
LCLLower Control Limit
OCAPOut-of-Control Action PlanDocumented steps when an SPC rule fires.
MRBMaterial Review BoardDecides what happens to held material: release, rework, scrap or deviation.
MIMMetal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal)Precision on-chip capacitors.
MOMMetal-Oxide-Metal (finger) capacitor
BSIMBerkeley Short-channel IGFET ModelIndustry-standard compact transistor model family used in design kits.
VtThreshold voltageGate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD.
IdsatSaturation drain currentId at Vgs = Vds = VDD, per µm of width; transistor strength.
IoffOff-state leakage currentId at Vgs = 0, Vds = VDD.
DIBLDrain-Induced Barrier LoweringVt drop per volt of Vds in short-channel devices.
SSSubthreshold swing (also SS = slow-slow process corner)mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature.
TTTypical-typical process cornerFF = fast-fast; FS / SF = skewed NMOS / PMOS corners.
FFFast-fast process corner
gmTransconductance∂Id/∂Vgs; the transistor's gain.
gdsOutput conductance∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds).
CoxGate-oxide capacitance per areaεox / Tox.
ToxGate-oxide thicknessMeasured with C-V structures in WAT.
fTTransit (unity current-gain) frequency≈ gm / 2π(Cgs + Cgd).
fmaxMaximum oscillation (unity power-gain) frequencyNeeds ≈ 3–4× the operating frequency for useful gain.
VbdGate-oxide breakdown voltageVoltage where oxide current jumps past compliance in a V-ramp test.
BVBreakdown VoltageBVdss = drain-source (gate off), BVj = junction.
BVdssDrain-source breakdown voltageTransistor off-state breakdown; limits PA drain swing.
BVjJunction breakdown voltageReverse breakdown of N+/P-well or P+/N-well diodes.
TLPTransmission-Line PulseESD device characterisation with short, high-current pulses.
QBDCharge to breakdownTotal charge an oxide passes before breaking down (reliability).
IMDInter-Metal DielectricInsulator between metal lines/layers; tested with comb structures.
CMPChemical-Mechanical PlanarizationPolishing step that flattens each layer; source of centre, edge and ring signatures.
OPCOptical Proximity CorrectionMask shape corrections; weak spots (hotspots) can fail per reticle shot.
EBREdge Bead RemovalRemoves resist build-up at the wafer edge.
D0Defect densityRandom defects per unit area; baseline yield Y ≈ e^(−D0·A).
HTOLHigh-Temperature Operating Life≈ 1000 h biased at max temperature (AEC-Q100).
ELFREarly Life Failure RateShort high-temperature operation of a large sample.
TCTemperature CyclingPackage and interconnect fatigue test.
THBTemperature-Humidity-Bias85 °C / 85% RH with bias.
HASTHighly Accelerated Stress Test130 °C / 85% RH with bias.
RHRelative Humidity
HTSLHigh-Temperature Storage LifeUnbiased bake.
HBMHuman-Body Model (ESD)
CDMCharged-Device Model (ESD)
LULatch-UpJESD78 test.
EMElectromigrationMetal wear-out under current (wafer-level reliability).
TDDBTime-Dependent Dielectric BreakdownGate-oxide wear-out.
HCIHot-Carrier InjectionTransistor degradation mechanism.
NBTINegative-Bias Temperature InstabilityPMOS threshold drift.

PCB, package & materials

Abbr.Stands forNote
TCBThermo-Compression BondingFlip-chip attach with heat and force per die; fine pitch, low warpage.
MUFMolded UnderfillMold compound that also fills the gap under a flip-chip die.
CSAMC-mode Scanning Acoustic MicroscopyUltrasound imaging of voids and delamination inside packages.
AOIAutomated Optical InspectionCamera inspection of RDL, bumps and balls in the assembly line.
KGDKnown-Good DieDie that passed wafer sort and is released for assembly.
WLPWafer-Level PackagePackage built on the whole wafer (fan-in) or a reconstituted wafer (fan-out).
PCBPrinted Circuit Board
RDLRedistribution LayerThin-film Cu wiring that routes die pads to balls (fan-out) or bumps.
UBMUnder-Bump MetallisationMetal stack between die/RDL pad and the solder.
FOWLPFan-Out Wafer-Level PackageDie embedded in mold with RDL fanning out to balls; eWLB is one type.
CSPChip-Scale PackagePackage only slightly larger than the die (FC-CSP = flip-chip CSP).
AiPAntenna-in-PackageAntennas built into package layers.
IMCIntermetallic CompoundLayer formed between solder and UBM/pad; grows with time and temperature.
CTECoefficient of Thermal ExpansionMismatch between materials drives solder and bump fatigue.
MSLMoisture Sensitivity LevelJ-STD-020 rating: how long a package may sit out of dry pack before reflow.
ELKExtreme Low-k dielectricFragile back-end dielectric in advanced nodes; cracks under bump stress.
NSMDNon-Solder-Mask-Defined padPCB pad style that improves solder-joint fatigue life.
DkDielectric constantSets line impedance and antenna tuning; shifts with moisture.
DfDissipation factorDielectric loss; key for RF loss at 77 GHz.
C-SAMC-mode Scanning Acoustic MicroscopyNon-destructive imaging of delamination and voids.
PBOPolybenzoxazolePolymer dielectric used in RDL (like polyimide).
EOSElectrical OverstressDamage from overvoltage or overcurrent beyond ESD events.
BGABall Grid ArrayFC-BGA = flip-chip BGA.
eWLBembedded Wafer-Level Ball-grid-arrayFan-out package with low RF loss.
AoPAntenna-on-Package
LoPLaunch-on-PackageRF launched from package into waveguide / antenna.
GCPWGrounded Coplanar WaveguidePCB transmission line at the ball launch.
SIWSubstrate-Integrated WaveguideWaveguide formed with via fences in the PCB.
FR4Flame-Retardant epoxy-glass laminateStandard low-cost PCB material.
ENEPIGElectroless Nickel, Electroless Palladium, Immersion GoldPCB surface finish.
ImAgImmersion SilverPCB surface finish.
HASLHot-Air Solder LevelingSurface finish; too rough/uneven for 77 GHz.
PBTPolybutylene terephthalate (PC = polycarbonate)Radome plastics.
HFSSHigh-Frequency Structure Simulator (Ansys)3D EM simulator (CST = Dassault's equivalent).