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Package, interconnect and failure modes
Package · reliabilityAt 77 GHz the package is part of the RF circuit. Every millimetre of redistribution line, every solder ball and every via on the way to the antenna adds loss and mismatch, and the same interconnects must survive 15+ years of temperature cycling in a bumper. This section covers the package types used for automotive radar, the dimensions of their interconnects (RDL, bumps, balls), the failure modes each one brings, and how they show up in radar test and in the field.
Package types in ADAS radar
| Package | How the die connects | Strengths | Watch-outs | Typical radar use |
|---|---|---|---|---|
| Fan-out WLP (eWLB / FOWLP) | Die embedded in mold; Cu RDL fans out to solder balls, no substrate | Shortest, lowest-loss RF path (no bump + substrate); thin; cost | Die-edge RDL stress, warpage, board-level solder fatigue on the balls | Single-chip 77 GHz radar SoCs (front and corner) |
| Flip-chip CSP / BGA | Cu pillar or solder bumps to an organic substrate, BGA balls to PCB | High pin count, good power delivery, thermal path | Bump / low-k cracking (chip-package interaction), substrate RF loss | Large radar SoCs with big DSP/memory, imaging radar processors |
| Antenna-in-package (AiP / AoP) | Antennas built into RDL or substrate layers | No RF on the PCB; small module | Antenna gain limited; moisture changes Dk/Df and detunes the antenna | Short-range radar, 60 GHz in-cabin sensing |
| Launch-on-package (LoP) | RF launched from the package into a waveguide or 3D antenna | Low loss, high antenna efficiency | Alignment and assembly tolerance; new interface to qualify | High-performance and imaging radars with waveguide antennas |
| Wire-bond (QFN) | Bond wires | Cheap, mature | Bond-wire inductance is far too large at 77 GHz | Only for PMIC, MCU and other non-RF chips on the module |
How these packages are built step by step (bumping, fan-out molding, RDL layers, ball attach, inspection) is on the assembly-flow page.
Interconnect dimensions (typical)
| Element | Typical size / pitch | RF and reliability notes |
|---|---|---|
| RDL line / space (fan-out) | 10/10 µm mainstream, down to 2–5 µm advanced; 1–3 Cu layers, 3–8 µm thick | RF lines built as grounded coplanar or microstrip in the RDL; line loss and impedance depend on dielectric thickness and Dk/Df |
| RDL dielectric | Polyimide / PBO or low-loss polymer, 5–15 µm per layer | Df at 77 GHz sets loss; moisture uptake shifts Dk and Df |
| RDL via | ≈ 10–30 µm diameter | Stacked vias at the die edge are a crack site in temperature cycling |
| UBM (under-bump metallisation) | Cu / Ni / Au stacks, a few µm | Sets intermetallic growth and electromigration robustness |
| Cu pillar bump (flip-chip) | Ø 25–50 µm, pitch 50–150 µm, solder cap on top | Stiff pillars pass more stress into the low-k layers under them |
| Solder bump (flip-chip) | Ø 70–100 µm, pitch 130–200 µm | More compliant; larger pitch |
| BGA / fan-out solder ball | Ø 0.25–0.3 mm at 0.4–0.5 mm pitch (fan-out); Ø 0.4–0.6 mm at 0.65–1.0 mm (BGA) | RF balls need a ground cage of neighbouring balls; corner balls fatigue first |
| Ball-to-PCB RF transition | ≈ 0.3–1 dB loss at 77 GHz when well designed | Pad, anti-pad and via fence co-designed with the package (see antenna & transition) |
Failure modes
| # | Failure mode | Mechanism / driver | Accelerating test | How it shows up in a radar | Mitigation |
|---|---|---|---|---|---|
| 1 | Solder-joint fatigue (board level) | CTE mismatch between package and PCB; each thermal cycle strains the ball, cracks grow at the intermetallic interface; corner balls first | Board-level temperature cycling (e.g. −40 ↔ 125 °C), power cycling | Intermittent open: an RF ball crack drops Tx power or raises reflected power; a supply ball crack causes resets | Ball size and pad design (NSMD), corner/edge underfill or glue, low-CTE PCB, keep RF balls away from corners |
| 2 | Bump crack / low-k (ELK) cracking | Chip-package interaction: CTE mismatch of die and substrate stresses bumps and the fragile low-k dielectric under them | Temperature cycling, reflow cycles | Open or high-resistance bumps; leakage if cracks reach the interconnect | Bump layout and polyimide stress buffer, underfill choice, crack-stop structures in the die |
| 3 | RDL / via crack at the die edge | Fan-out: the RDL crosses from stiff silicon to compliant mold; stress concentrates at the edge and at stacked vias | Temperature cycling | Rising resistance, then open; on an RF line, extra loss and lower Tx power | Routing rules at the die edge, avoid stacked vias there, thicker Cu, stress-relief dielectric |
| 4 | Delamination (mold–die, dielectric–RDL, underfill) | Moisture absorbed before reflow turns to steam (popcorn); poor adhesion; thermal mismatch | Moisture preconditioning (MSL) + reflow, then TC / HAST; detected by C-SAM | Cracks that lead to opens; moisture path for corrosion; RF dielectric change | MSL rating and dry-pack, baking, adhesion promoters, mold compound choice |
| 5 | Warpage | Mismatch between mold, die and RDL; worse for large or thin packages | Shadow-moiré measurement over the reflow profile | Non-wet opens and head-in-pillow joints at board assembly | Mold CTE and thickness, carrier, coplanarity spec, reflow profile |
| 6 | Electromigration in bumps / RDL | High current density at high temperature moves metal atoms and forms voids | EM test at high current and temperature | Resistance rise on supply bumps (PA and digital rails), then open | Current-density limits, more bumps per rail, UBM choice |
| 7 | Intermetallic growth / Kirkendall voids | Long time at high temperature thickens the solder–UBM intermetallic and forms voids | HTSL (high-temperature storage) | Brittle joints that crack later under vibration or cycling | UBM with a Ni barrier, solder alloy, temperature derating |
| 8 | Corrosion / electrochemical migration | Humidity + bias + ionic contamination (flux residue); bumper environment with salt and condensation | THB / HAST, bias humidity | Leakage and shorts between balls; drifting pin leakage at test | Cleanliness, conformal coating or sealed housing, pitch and bias rules |
| 9 | Die crack / chipping | Dicing damage, handling, thin die under stress | TC, mechanical shock | Opens or leakage, sometimes latent | Dicing process control, die-edge inspection, crack-stop rings |
| 10 | RF drift of the package | Moisture absorption and ageing change Dk/Df of mold and RDL dielectric; transition geometry shifts | 85 °C / 85 % RH soak with RF re-measurement | Lower Tx power, higher NF; in AiP, antenna detuning and beam shift | Low-moisture, low-loss materials; margin in the link budget; runtime Tx power loop and monitors |
| 11 | ESD / EOS at RF pads during assembly | Handling and assembly discharges into LNA / PA pads, which have light ESD protection to keep capacitance low | HBM / CDM testing; process audits | Higher NF, lower gain, leakage on RF pins | ESD control in assembly, pad protection design, CDM targets |
Catching package defects at test
- Final test after assembly: open/short and Cres catch hard opens and shorts; the RF balls use the inverted-logic check. Parametric leakage finds corrosion paths and ESD damage.
- RF BIST: Tx power and the reflected-power detector (BIST path A) reveal a cracked or high-loss RF path through the package even when DC continuity passes.
- Non-destructive inspection: X-ray for voids and bridging, C-SAM (scanning acoustic microscopy) for delamination, shadow-moiré for warpage, sampled from production.
- Destructive analysis: cross-sections and dye-and-pry on reliability samples and field returns to locate cracks.
- In the field: the Tx power loop and safety monitors (Tx power control) flag a slow degradation before it becomes a failure.
Qualification conditions, pass criteria and the physical analysis after stress (CSAM, X-ray, cross-section) are on the qualification page.
What today's ADAS market asks of the package
| Trend / requirement | Consequence for the package |
|---|---|
| Mission profile: 15+ years, −40…+125 °C ambient in the bumper (AEC-Q100 Grade 1; some ask Grade 0) | Board-level temperature cycling beyond component qualification, commonly 1000–3000 cycles at −40 ↔ 125 °C per OEM spec; qualification per AEC-Q100, and AEC-Q104 for multi-chip modules |
| More radars per car (front + 4 corners, plus in-cabin) under cost pressure | Fan-out packages without a substrate and high-volume assembly; package cost counts per sensor |
| 4D imaging radar: several cascaded chips or one large SoC | Bigger packages and boards; matched LO routing between chips; flip-chip packages for large processors, with more bump and warpage risk |
| Higher antenna efficiency: waveguide and 3D antennas | Launch-on-package interfaces to qualify; tight assembly tolerances |
| In-cabin sensing (e.g. child presence detection at 60 GHz) | Antenna-in-package modules; RF drift with humidity matters because there's no PCB antenna margin |
| Satellite radar architecture (raw data to a central ECU) | Simpler front-end chips, but high-speed data interfaces through the package |
| Advanced RFCMOS nodes (28/22 nm and below) with more digital content | Larger die, more bumps, fragile low-k: chip-package interaction becomes a design rule, not an afterthought |
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Glossary of abbreviations
Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.
Radar system & ADAS
| Abbr. | Stands for | Note |
|---|---|---|
| FCW | Forward Collision Warning | Warns of an imminent frontal collision; stage before AEB. |
| FCTA | Front Cross-Traffic Alert | Front corner-radar function at junctions and driveways. |
| RCTB | Rear Cross-Traffic Braking | Brakes automatically when RCTA detects cross traffic while reversing. |
| DOW | Door-Opening Warning | Warns before a door is opened into an approaching cyclist or car. |
| VRU | Vulnerable Road User | Pedestrians, cyclists and motorcyclists. |
| TTC | Time To Collision | Range divided by closing speed; triggers warnings and braking. |
| LRR | Long-Range Radar | Front radar, ≈ 200–300 m, narrow field of view. |
| MRR | Mid-Range Radar | ≈ 80–160 m, ±40–60° field of view. |
| SRR | Short-Range Radar | Corner radar, ≈ 30–80 m, ±75–90° field of view. |
| NCAP | New Car Assessment Programme | Consumer safety ratings (Euro NCAP, C-NCAP, IIHS …). |
| GSR | General Safety Regulation (EU) 2019/2144 | Makes AEB and other assistance functions mandatory in the EU. |
| CPD | Child Presence Detection | In-cabin sensing (often 60 GHz radar) that detects a child left in the car. |
| ACC | Adaptive Cruise Control | Keeps distance to the car ahead; uses long-range front radar. |
| ADAS | Advanced Driver-Assistance Systems | The vehicle functions the radar serves. |
| AEB | Autonomous Emergency Braking | Brakes automatically when a collision is imminent. |
| BSD | Blind-Spot Detection | Corner-radar function. |
| LCA | Lane-Change Assist | Corner-radar function that warns of fast approaching vehicles. |
| RCTA | Rear Cross-Traffic Alert | Rear corner-radar function when reversing. |
| L2 | SAE automation Level 2 (L3 = Level 3) | Partial (L2) and conditional (L3) driving automation. |
| FMCW | Frequency-Modulated Continuous Wave | A linear chirp; range comes from the beat frequency f_b = S·2R/c. |
| FoV | Field of View | Angular coverage in azimuth and elevation. |
| RCS | Radar Cross Section | Target reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0). |
| dBsm | Decibels relative to 1 m² | Unit of RCS. |
| EIRP | Effective Isotropic Radiated Power | Tx power + antenna gain; limited by regulations. |
| MIMO | Multiple-Input Multiple-Output | N_tx × N_rx channels form a larger virtual array. |
| TDM | Time-Division Multiplexing | One Tx per chirp; v_max falls by a factor of N_tx. |
| BPM | Binary Phase Modulation | 0/180° codes across chirps separate the Tx signals. |
| DDMA | Doppler-Division Multiple Access | Each Tx gets a slow-time phase ramp and separates in Doppler. |
| DoA | Direction of Arrival | Angle estimation over the virtual array. |
| DBF | Digital Beamforming | FFT or matched steering over array channels. |
| CFAR | Constant False Alarm Rate | Adaptive detection threshold (CA = cell-averaging, OS = ordered-statistic). |
| FFT | Fast Fourier Transform | Range, Doppler and angle FFTs build the radar cube. |
| SNR | Signal-to-Noise Ratio | |
| MUSIC | MUltiple SIgnal Classification | Subspace super-resolution DoA algorithm. |
| ESPRIT | Estimation of Signal Parameters via Rotational Invariance Techniques | Super-resolution DoA algorithm. |
| IAA | Iterative Adaptive Approach | Super-resolution spectral / DoA estimator. |
| DBSCAN | Density-Based Spatial Clustering of Applications with Noise | Groups detections into objects. |
| EKF | Extended Kalman Filter | Nonlinear tracking filter. |
| UKF | Unscented Kalman Filter | Nonlinear tracking filter using sigma points. |
| IMM | Interacting Multiple Model | Tracker that mixes several motion models. |
| HWA | Hardware Accelerator | On-chip FFT / radar processing engine. |
| RTS | Radar Target Simulator | Echo generator for HIL and EOL testing. |
| HIL | Hardware-in-the-Loop | Testing the real sensor against simulated scenarios. |
| EOL | End-of-Line | Final production test of a module or vehicle. |
RF & analog front end
| Abbr. | Stands for | Note |
|---|---|---|
| HPBW | Half-Power Beamwidth | Angle between the −3 dB points of an antenna or array beam. |
| PDN | Power Delivery Network | Regulators, planes, decoupling and package paths that supply the chip. |
| PI | Power Integrity | Keeping supply voltage within limits under load steps and noise. |
| EMI | Electromagnetic Interference | Unwanted emission or pick-up of electromagnetic energy. |
| BCI | Bulk Current Injection | Immunity test (ISO 11452-4) that injects RF current into a cable harness. |
| TIM | Thermal Interface Material | Gap pad or paste between board or package and the heat sink. |
| RF | Radio Frequency | Here the 76–81 GHz signal. |
| LO | Local Oscillator | The chirp signal that drives the Tx and the Rx mixers. |
| IF | Intermediate Frequency | The beat / baseband signal after the mixer, DC–20 MHz. |
| PA | Power Amplifier | Tx output stage, 12–14 dBm. |
| LNA | Low-Noise Amplifier | First Rx stage; sets most of the NF. |
| NF | Noise Figure | Noise the receiver adds, in dB. |
| VGA | Variable-Gain Amplifier | Programmable-gain stage (IF), or signed VGAs in the phase rotator. |
| TIA | Transimpedance Amplifier | Current-to-voltage stage after a passive mixer. |
| HPF | High-Pass Filter | In IF: removes leakage and DC, and equalises R⁻⁴. |
| LPF | Low-Pass Filter | |
| AAF | Anti-Aliasing Filter | Low-pass filter in front of the ADC. |
| PPF | Polyphase Filter | RC-CR network that generates I/Q. |
| I/Q | In-phase / Quadrature | Two copies of a signal 90° apart. |
| IRR | Image Rejection Ratio | How well an I/Q path suppresses the mirror frequency. |
| SSB | Single Sideband | A frequency shift in one direction only, e.g. the loopback offset. |
| BPSK | Binary Phase-Shift Keying | 0/180° switching; produces ±f_m sidebands. |
| VM | Vector Modulator | I/Q-weighted phase rotator. |
| RTPS | Reflection-Type Phase Shifter | Hybrid coupler terminated by tunable loads. |
| P1dB | 1 dB compression point | Input (or output) level where gain drops by 1 dB. |
| IIP3 | Input third-order intercept point | Linearity figure; cascades with the gain before each stage. |
| PAE | Power-Added Efficiency | (P_out − P_in) / P_DC of a PA. |
| Psat | Saturated output power | Maximum output power of a PA. |
| DSB | Double Sideband | Noise figure counting both sidebands (typical for zero-IF mixers). |
| PGA | Programmable-Gain Amplifier | IF VGA with digitally set gain steps. |
| AGC | Automatic Gain Control | Loop that sets the VGA gain from the signal level. |
| HD2 | 2nd-order Harmonic Distortion (HD3 = 3rd) | Harmonics show up as ghost targets at 2×/3× range. |
| AM/PM | Amplitude-to-phase conversion | Phase change caused by amplitude or supply changes. |
| RL | Return Loss | Match quality, in dB. |
| Cpl | Coupler (directional coupler) | Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback. |
| PD | Power Detector | Diode or square-law RF-to-DC converter. |
| APC | Automatic Power Control | Closed loop from the power detector to the VGA/PA gain code. |
| DPD | Digital Predistortion | Wideband PA linearisation used in comms; radar uses static gain/phase LUTs instead. |
| VSWR | Voltage Standing-Wave Ratio | Mismatch at the antenna/load; changes the delivered power. |
| CW | Continuous Wave | An unmodulated single-frequency tone. |
| ENR | Excess Noise Ratio | Calibrated output level of a noise source. |
| SiGe | Silicon-Germanium (BiCMOS) | Bipolar-plus-CMOS process used for earlier radar chips. |
| CMOS | Complementary Metal-Oxide-Semiconductor | RFCMOS = CMOS process with RF / mmWave capability. |
| RFCMOS | RF-capable CMOS | Today's single-chip radar process (e.g. 45/40/28/22 nm). |
| NMOS | N-channel MOS transistor (PMOS = P-channel) | |
| PTAT | Proportional To Absolute Temperature | Voltage or current used by temperature sensors. |
| BG | Bandgap reference | Temperature-stable voltage reference (BG1/BG2 = two independent ones). |
| PVT | Process, Voltage, Temperature | Variation corners a design must cover. |
LO, clock & synthesis
| Abbr. | Stands for | Note |
|---|---|---|
| PLL | Phase-Locked Loop | Locks the VCO to the crystal and generates the ramp. |
| ADPLL | All-Digital PLL | PLL with a TDC and a digital loop filter. |
| VCO | Voltage-Controlled Oscillator | ≈ 19–20.25 GHz, multiplied ×4 to 77 GHz. |
| PFD | Phase-Frequency Detector | Compares the divided VCO with the reference. |
| CP | Charge Pump; also Chip Probe | In a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test. |
| TDC | Time-to-Digital Converter | Digital phase detector of an ADPLL. |
| XTAL | Crystal (reference oscillator) | 40/50 MHz reference for PLL, ADC and digital. |
| DDS | Direct Digital Synthesizer | Digitally generated tone (IF test tone). |
| Kvco | VCO gain | Tuning sensitivity in MHz/V; varies per band. |
| AFC | Automatic Frequency Calibration (band calibration) | Picks the VCO capacitor-bank band before the PLL closes. |
| MMD | Multi-Modulus Divider | Programmable divider in the PLL feedback, dithered by the ΣΔ modulator. |
| CML | Current-Mode Logic | Fast differential logic used for the first divider (prescaler) stages at 20 GHz. |
Data conversion & digital
| Abbr. | Stands for | Note |
|---|---|---|
| SNM | Static Noise Margin | Noise an SRAM cell tolerates before flipping; read SNM is the critical one. |
| SEU | Single-Event Upset | Bit flip caused by a particle strike (soft error). |
| SER | Soft-Error Rate | Rate of radiation-induced bit flips, in FIT per Mbit. |
| MBU | Multi-Bit Upset | One particle flips several neighbouring cells. |
| RDF | Random Dopant Fluctuation | Random number of dopant atoms in a small channel; main cause of Vth mismatch. |
| LER | Line-Edge Roughness | Rough gate edges that add Vth variation in small devices. |
| NPSF | Neighbourhood Pattern-Sensitive Fault | Memory cell fails only for certain data in its neighbours. |
| SEC-DED | Single-Error Correction, Double-Error Detection | ECC code used on memory words (e.g. 64 + 8 bits). |
| ROM | Read-Only Memory | Mask-programmed memory for boot code and tables. |
| DRF | Data-Retention Fault | Memory cell loses its value after a pause. |
| WL | Word Line | Row select line of a memory array. |
| BL | Bit Line | Column data line of a memory array (BL and its complement BLB). |
| OSR | Oversampling Ratio | fs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR. |
| NTF | Noise Transfer Function | How a ΣΔ loop shapes quantisation noise out of the signal band. |
| SNDR | Signal-to-Noise-and-Distortion Ratio | ENOB = (SNDR − 1.76) / 6.02. |
| GBW | Gain-Bandwidth product | Op-amp figure of merit; sets filter and PGA accuracy at IF. |
| CMRR | Common-Mode Rejection Ratio | How well a differential circuit rejects signals common to both inputs. |
| CSI-2 | MIPI Camera Serial Interface 2 | High-speed serial link used for raw radar data. |
| TSN | Time-Sensitive Networking | Deterministic automotive Ethernet (IEEE 802.1). |
| ADC | Analog-to-Digital Converter | Main Rx ADCs (ΣΔ) and the aux SAR ADC. |
| DAC | Digital-to-Analog Converter | Rotator I/Q weights, bias, trim, test-tone generation. |
| SAR | Successive-Approximation Register ADC | Slow, precise ADC used for monitoring. |
| CT | Continuous-Time (CT-ΣΔ) | Sigma-delta ADC with a continuous-time loop filter. |
| ENOB | Effective Number of Bits | |
| SFDR | Spurious-Free Dynamic Range | Tone relative to the largest spur. |
| THD | Total Harmonic Distortion | |
| DR | Dynamic Range | |
| INL | Integral Nonlinearity | Deviation from the ideal transfer line. |
| DNL | Differential Nonlinearity | Deviation of each step from 1 LSB. |
| LSB | Least Significant Bit (MSB = most significant) | |
| DFE | Digital Front End | Decimation, DC and I/Q correction, interference handling. |
| CIC | Cascaded Integrator-Comb | Multiplier-free decimation filter. |
| FIR | Finite Impulse Response filter | |
| DSP | Digital Signal Processor | |
| MCU | Microcontroller Unit | |
| CPU | Central Processing Unit | E.g. the RF control CPU that runs chirps and monitors. |
| SoC | System-on-Chip | |
| ECU | Electronic Control Unit | Vehicle computer that receives radar data. |
| SRAM | Static RAM (RAM = random-access memory) | |
| ECC | Error-Correcting Code | Memory protection for functional safety. |
| DMA | Direct Memory Access | |
| LUT | Look-Up Table | E.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature. |
| FW | Firmware (SW = software) | |
| OTP | One-Time Programmable memory | Holds trims and IDs, like eFuse. |
| SPI | Serial Peripheral Interface | Configuration / test bus from host or ATE. |
| CAN | Controller Area Network (CAN-FD = Flexible Data-rate) | Vehicle bus for object lists. |
| ETH | Ethernet (100/1000BASE-T1) | Automotive single-pair Ethernet. |
| CSI | Camera Serial Interface (MIPI CSI-2) | Streams raw radar data to a central SoC. |
| LVDS | Low-Voltage Differential Signaling | Raw-data debug / streaming interface. |
| GPIO | General-Purpose Input/Output | |
| IO | Input/Output |
Power
| Abbr. | Stands for | Note |
|---|---|---|
| LDO | Low-Dropout regulator | Linear regulator; one per noise-sensitive domain. |
| PMIC | Power-Management IC | External bucks, supervisors and watchdog. |
| PSRR | Power-Supply Rejection Ratio | How much supply ripple an LDO (or circuit) blocks. |
| UV | Under-Voltage (OV = Over-Voltage) | Supply monitors, a safety mechanism. |
| OV | Over-Voltage | Rail above its window; OV monitor protects gate oxides. |
| POR | Power-On Reset | Holds the chip in reset until all rails are valid. |
| BOR | Brown-Out Reset | Resets when a supply sags during operation. |
| ESR | Equivalent Series Resistance | Of the LDO output capacitor; its zero affects loop stability. |
| OCP | Over-Current Protection | Current limit on a regulator output. |
| Iq | Quiescent current | Current a regulator draws for itself with no load. |
| DLDO | Digital LDO | Switched pass-device array regulated by a comparator loop. |
| GND | Ground |
Test & production
| Abbr. | Stands for | Note |
|---|---|---|
| EVB | Evaluation Board | Board that carries the chip on the bench with supplies, clock, interfaces and RF transitions. |
| SMU | Source-Measure Unit | Precision instrument that forces voltage or current and measures the other. |
| OTA | Over The Air | Measurement through antennas in a chamber instead of a cable or waveguide. |
| GSG | Ground-Signal-Ground probe | RF wafer probe with a signal tip between two ground tips. |
| LRRM | Line-Reflect-Reflect-Match calibration | On-wafer VNA calibration method for mmWave probes. |
| SCPI | Standard Commands for Programmable Instruments | Text command set used to automate instruments. |
| UPH | Units Per Hour | Test throughput of a tester and handler. |
| eFuse | Electrically programmable fuse | Silicided poly link blown by current; stores trim, ID and repair bits. |
| MTP | Multiple-Time Programmable memory | Small NVM that can be rewritten a few times. |
| NVM | Non-Volatile Memory | Keeps data without power: eFuse, OTP, MTP, flash. |
| VPP | Programming supply voltage | Supply used only to program fuses or OTP. |
| CRC | Cyclic Redundancy Check | Checksum that detects corrupted data, e.g. trim words at boot. |
| RMA | Return Material Authorization | A customer return, analysed through the 8D process. |
| 8D | Eight Disciplines | Structured problem solving: team, describe, contain, root cause, correct, verify, prevent, close. |
| MSA | Measurement System Analysis | Proves a measurement is precise and accurate enough (Gage R&R, bias, stability). |
| GRR | Gage Repeatability and Reproducibility | %GRR < 10 % of tolerance is good. |
| BIST | Built-In Self-Test | On-chip stimulus + measurement; result is pass/fail or a value checked against a limit. |
| BISM | Built-In Self-Measurement | Same on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend. |
| DFT | Design for Test | |
| ATE | Automatic Test Equipment | Production tester. |
| ATPG | Automatic Test Pattern Generation | Scan patterns for digital logic. |
| IDDQ | Quiescent supply-current test | Detects leakage defects. |
| PMU | Parametric Measurement Unit | ATE DC source/measure channel. |
| Cres | Contact resistance | Probe or socket contact resistance; measured with the Kelvin or two-current method. |
| FIMV | Force Current, Measure Voltage | PMU mode used for open/short (diode) tests. |
| FVMI | Force Voltage, Measure Current | PMU mode used for leakage and power-short tests. |
| IIL | Input leakage current, input Low (IIH = input High) | Leakage limit per IO pin, typically |I| < 1 µA. |
| IIH | Input leakage current, input High | |
| ESD | Electrostatic Discharge | Pad protection diodes / clamps; the diode method uses them for continuity. |
| VDD | Positive supply rail (VSS = ground / negative rail) | |
| VSS | Ground / negative supply rail | |
| DCR | DC Resistance | E.g. of an RF shunt inductor, 0.5–3 Ω. |
| Hi-Z | High impedance (Z) | Output driver switched off; the pin floats. |
| OE | Output Enable | Control that switches an output between driving and Hi-Z. |
| IOZ | Off-state output leakage (IOZH at VDDIO, IOZL at 0 V) | Measured on a pin in Hi-Z; typically |I| < 1–10 µA. |
| VOH | Output High voltage threshold (VOL = Output Low) | Tester comparator levels that decide 1 / Z / 0. |
| VOL | Output Low voltage threshold | |
| HIGHZ | IEEE 1149.1 instruction that puts all outputs in Hi-Z | |
| EXTEST | IEEE 1149.1 external test instruction | Boundary cells drive and sample the pins; used for interconnect and walking-Z tests. |
| RPCT | Reduced Pin-Count Testing | Testing through JTAG / a few pins, so more sites fit on one tester. |
| BICS | Built-In Current Sensor | On-chip current monitor for IDDQ per power domain. |
| SPC | Statistical Process Control | |
| VNA | Vector Network Analyzer | Lab instrument for S-parameters. |
| AWG | Arbitrary Waveform Generator | |
| DMM | Digital Multimeter | |
| GPIB | General-Purpose Interface Bus | Instrument control bus (like LAN). |
Safety, standards & regulation
| Abbr. | Stands for | Note |
|---|---|---|
| PMHF | Probabilistic Metric for random Hardware Failures | ISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D. |
| SEooC | Safety Element out of Context | A part developed to ISO 26262 against assumed system requirements. |
| FMEA | Failure Mode and Effects Analysis | Qualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage. |
| FIT | Failures In Time | Failures per 10⁹ device-hours. |
| MTTF | Mean Time To Failure | |
| RED | Radio Equipment Directive (EU 2014/53/EU) | EU conformity framework for radio transmitters, including radar. |
| ASIL | Automotive Safety Integrity Level | ISO 26262 risk class A–D; radar typically ASIL-B. |
| ISO | ISO 26262 / ISO/SAE 21434 / ISO 11452 | Functional safety / cybersecurity / EMC immunity. |
| FTTI | Fault-Tolerant Time Interval | Time from fault to hazard; monitors must react within it. |
| FMEDA | Failure Modes, Effects and Diagnostic Analysis | |
| SPFM | Single-Point Fault Metric | ISO 26262 coverage metric. |
| LFM | Latent Fault Metric | ISO 26262 coverage metric. |
| AEC | Automotive Electronics Council (AEC-Q100 / Q200) | Qualification of ICs / passives. |
| ETSI | European Telecommunications Standards Institute | EN 301 091 / EN 303 396 radar standards. |
| FCC | Federal Communications Commission | US rules, Part 95M for 76–81 GHz. |
| EMC | Electromagnetic Compatibility | |
| CISPR | Comité International Spécial des Perturbations Radioélectriques | CISPR 25: vehicle-component emissions. |
| OOB | Out-of-Band (emission) |
Digital DFT, stress & reliability
| Abbr. | Stands for | Note |
|---|---|---|
| UHST | Unbiased Highly Accelerated Stress Test | HAST without bias, 130 °C / 85 % RH; alternative to autoclave. |
| PTC | Power Temperature Cycling | Temperature cycling with the device powered on and off. |
| EDR | Endurance and Data Retention | Qualification of non-volatile memory (AEC-Q100-005). |
| DPA | Destructive Physical Analysis | Opening and sectioning parts to inspect their construction and damage. |
| SEM | Scanning Electron Microscope | High-magnification imaging of cross-sections and surfaces. |
| EDX | Energy-Dispersive X-ray spectroscopy | Element analysis in the SEM: corrosion, contamination, IMC phases. |
| FIB | Focused Ion Beam | Precise local cutting and imaging; also used for circuit edits. |
| LTPD | Lot Tolerance Percent Defective | Defect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %. |
| PC | Preconditioning | Bake, moisture soak and reflow before environmental stress (JESD22-A113). |
| BLR | Board-Level Reliability | Reliability of the package soldered on a PCB (temperature cycling, drop, vibration). |
| SAC | Tin-Silver-Copper solder | Lead-free solder alloy (e.g. SAC305) used for balls. |
| PPAP | Production Part Approval Process | Automotive approval package, includes the qualification report. |
| DRC | Design Rule Check | Verifies layout against foundry manufacturing rules. |
| LVS | Layout Versus Schematic | Verifies that the layout matches the schematic netlist. |
| PEX | Parasitic Extraction | Extracts resistance, capacitance (and inductance) of the layout for post-layout simulation. |
| AMS | Analog / Mixed-Signal simulation | Simulation that combines transistor-level analog with digital models. |
| ECO | Engineering Change Order | Late design fix; a metal-only ECO changes only upper masks. |
| SCR | Silicon-Controlled Rectifier | Thyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up. |
| GGNMOS | Grounded-Gate NMOS | ESD clamp that works by parasitic-bipolar snapback. |
| SE | Scan Enable | Selects shift (SE = 1) or functional capture (SE = 0) in scan flops. |
| SAF | Stuck-At Fault | Node permanently 0 or 1. |
| TDF | Transition Delay Fault | Node slow to rise or fall; needs at-speed test. |
| STA | Static Timing Analysis | Finds the longest paths for timing-aware ATPG. |
| OCV | On-Chip Variation | Timing derates in STA that account for local (mismatch) variation across the die. |
| OCC | On-Chip Clock Controller | Gates exact launch/capture pulses from the PLL for at-speed test. |
| LOC | Launch-On-Capture | At-speed scheme; also called broadside. |
| LOS | Launch-On-Shift | At-speed scheme; SE must switch at speed. |
| EDT | Embedded Deterministic Test | Scan compression (decompressor + compactor). |
| LFSR | Linear-Feedback Shift Register | Pseudo-random sequence generator. |
| PRPG | Pseudo-Random Pattern Generator | LFSR that feeds the scan chains in LBIST. |
| MISR | Multiple-Input Signature Register | Compresses responses into one signature. |
| STUMPS | Self-Test Using MISR and Parallel Shift-register sequence generator | Standard LBIST architecture. |
| LBIST | Logic BIST | On-chip random-pattern scan test; used at key-on. |
| MBIST | Memory BIST | On-chip March-algorithm test of SRAMs. |
| BIRA | Built-In Redundancy Analysis | Computes which spare rows/columns repair a memory. |
| BISR | Built-In Self-Repair | Loads the repair from eFuse at boot. |
| IR | IR drop | Supply voltage drop (current × resistance), high during scan shift. |
| JTAG | Joint Test Action Group (IEEE 1149.1) | Boundary scan and test access port. |
| TAP | Test Access Port | JTAG pins TCK, TMS, TDI, TDO, TRST. |
| BSDL | Boundary Scan Description Language | Describes a chip's JTAG boundary-scan cells. |
| IJTAG | Internal JTAG (IEEE 1687) | Network for accessing on-chip instruments. |
| MUX | Multiplexer | Selects one of N inputs; in test, routes sub-block nodes to shared instruments. |
| ATB | Analog Test Bus | Chip-wide wire pair (force + sense) that test muxes connect sub-block nodes to. |
| TG | Transmission Gate | Parallel NMOS + PMOS switch; passes the full voltage range. |
| SPDT | Single-Pole Double-Throw switch | One input to one of two outputs (SP4T = one of four). |
| BBM | Break-Before-Make | Switching order that opens the old path before closing the new one. |
| ICL | Instrument Connectivity Language (PDL = Procedural Description Language) | IJTAG description files. |
| ECID | Electronic Chip ID | Unique per-die ID for traceability. |
| HVST | High-Voltage Stress Test | Short over-voltage on the core rail to activate latent oxide defects. |
| VLV | Very-Low-Voltage test | Test below nominal V to expose resistive defects. |
| Vmin | Minimum operating voltage | The pass/fail edge in a shmoo; an outlier Vmin flags a defect. |
| PAT | Part Average Testing (AEC-Q001) | Outlier limits at robust μ ± 6σ. |
| DPAT | Dynamic Part Average Testing | PAT limits recalculated per lot or wafer. |
| GDBN | Good Die in Bad Neighbourhood | Wafer-map screen that rejects dies in defect clusters. |
| NNR | Nearest-Neighbour Residual | Compares a die's parameter with its wafer neighbours. |
| DPPM | Defective Parts Per Million | Shipped-quality metric; automotive target ≪ 1. |
| FT | Final Test | Package-level production test. |
| SLT | System-Level Test | Functional test by booting the application. |
| PCM | Process Control Monitor | Test structures in the scribe lines, measured by the fab (see WAT). |
| WAT | Wafer Acceptance Test | Fab's electrical test of PCM structures before shipping wafers. |
| OSAT | Outsourced Semiconductor Assembly and Test | Company that packages and tests the dies. |
| QA | Quality Assurance | Sample-based outgoing inspection and audits. |
| Cp | Process capability (Cp) | (USL − LSL) / 6σ: spec width vs process spread. |
| Cpk | Process capability index | min(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67. |
| USL | Upper Spec Limit (LSL = Lower Spec Limit) | Design limits; outside them the part is out of spec. |
| LSL | Lower Spec Limit | |
| UCL | Upper Control Limit (LCL = Lower Control Limit) | Process limits from history, usually mean ± 3σ. |
| LCL | Lower Control Limit | |
| OCAP | Out-of-Control Action Plan | Documented steps when an SPC rule fires. |
| MRB | Material Review Board | Decides what happens to held material: release, rework, scrap or deviation. |
| MIM | Metal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal) | Precision on-chip capacitors. |
| MOM | Metal-Oxide-Metal (finger) capacitor | |
| BSIM | Berkeley Short-channel IGFET Model | Industry-standard compact transistor model family used in design kits. |
| Vt | Threshold voltage | Gate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD. |
| Idsat | Saturation drain current | Id at Vgs = Vds = VDD, per µm of width; transistor strength. |
| Ioff | Off-state leakage current | Id at Vgs = 0, Vds = VDD. |
| DIBL | Drain-Induced Barrier Lowering | Vt drop per volt of Vds in short-channel devices. |
| SS | Subthreshold swing (also SS = slow-slow process corner) | mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature. |
| TT | Typical-typical process corner | FF = fast-fast; FS / SF = skewed NMOS / PMOS corners. |
| FF | Fast-fast process corner | |
| gm | Transconductance | ∂Id/∂Vgs; the transistor's gain. |
| gds | Output conductance | ∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds). |
| Cox | Gate-oxide capacitance per area | εox / Tox. |
| Tox | Gate-oxide thickness | Measured with C-V structures in WAT. |
| fT | Transit (unity current-gain) frequency | ≈ gm / 2π(Cgs + Cgd). |
| fmax | Maximum oscillation (unity power-gain) frequency | Needs ≈ 3–4× the operating frequency for useful gain. |
| Vbd | Gate-oxide breakdown voltage | Voltage where oxide current jumps past compliance in a V-ramp test. |
| BV | Breakdown Voltage | BVdss = drain-source (gate off), BVj = junction. |
| BVdss | Drain-source breakdown voltage | Transistor off-state breakdown; limits PA drain swing. |
| BVj | Junction breakdown voltage | Reverse breakdown of N+/P-well or P+/N-well diodes. |
| TLP | Transmission-Line Pulse | ESD device characterisation with short, high-current pulses. |
| QBD | Charge to breakdown | Total charge an oxide passes before breaking down (reliability). |
| IMD | Inter-Metal Dielectric | Insulator between metal lines/layers; tested with comb structures. |
| CMP | Chemical-Mechanical Planarization | Polishing step that flattens each layer; source of centre, edge and ring signatures. |
| OPC | Optical Proximity Correction | Mask shape corrections; weak spots (hotspots) can fail per reticle shot. |
| EBR | Edge Bead Removal | Removes resist build-up at the wafer edge. |
| D0 | Defect density | Random defects per unit area; baseline yield Y ≈ e^(−D0·A). |
| HTOL | High-Temperature Operating Life | ≈ 1000 h biased at max temperature (AEC-Q100). |
| ELFR | Early Life Failure Rate | Short high-temperature operation of a large sample. |
| TC | Temperature Cycling | Package and interconnect fatigue test. |
| THB | Temperature-Humidity-Bias | 85 °C / 85% RH with bias. |
| HAST | Highly Accelerated Stress Test | 130 °C / 85% RH with bias. |
| RH | Relative Humidity | |
| HTSL | High-Temperature Storage Life | Unbiased bake. |
| HBM | Human-Body Model (ESD) | |
| CDM | Charged-Device Model (ESD) | |
| LU | Latch-Up | JESD78 test. |
| EM | Electromigration | Metal wear-out under current (wafer-level reliability). |
| TDDB | Time-Dependent Dielectric Breakdown | Gate-oxide wear-out. |
| HCI | Hot-Carrier Injection | Transistor degradation mechanism. |
| NBTI | Negative-Bias Temperature Instability | PMOS threshold drift. |
PCB, package & materials
| Abbr. | Stands for | Note |
|---|---|---|
| TCB | Thermo-Compression Bonding | Flip-chip attach with heat and force per die; fine pitch, low warpage. |
| MUF | Molded Underfill | Mold compound that also fills the gap under a flip-chip die. |
| CSAM | C-mode Scanning Acoustic Microscopy | Ultrasound imaging of voids and delamination inside packages. |
| AOI | Automated Optical Inspection | Camera inspection of RDL, bumps and balls in the assembly line. |
| KGD | Known-Good Die | Die that passed wafer sort and is released for assembly. |
| WLP | Wafer-Level Package | Package built on the whole wafer (fan-in) or a reconstituted wafer (fan-out). |
| PCB | Printed Circuit Board | |
| RDL | Redistribution Layer | Thin-film Cu wiring that routes die pads to balls (fan-out) or bumps. |
| UBM | Under-Bump Metallisation | Metal stack between die/RDL pad and the solder. |
| FOWLP | Fan-Out Wafer-Level Package | Die embedded in mold with RDL fanning out to balls; eWLB is one type. |
| CSP | Chip-Scale Package | Package only slightly larger than the die (FC-CSP = flip-chip CSP). |
| AiP | Antenna-in-Package | Antennas built into package layers. |
| IMC | Intermetallic Compound | Layer formed between solder and UBM/pad; grows with time and temperature. |
| CTE | Coefficient of Thermal Expansion | Mismatch between materials drives solder and bump fatigue. |
| MSL | Moisture Sensitivity Level | J-STD-020 rating: how long a package may sit out of dry pack before reflow. |
| ELK | Extreme Low-k dielectric | Fragile back-end dielectric in advanced nodes; cracks under bump stress. |
| NSMD | Non-Solder-Mask-Defined pad | PCB pad style that improves solder-joint fatigue life. |
| Dk | Dielectric constant | Sets line impedance and antenna tuning; shifts with moisture. |
| Df | Dissipation factor | Dielectric loss; key for RF loss at 77 GHz. |
| C-SAM | C-mode Scanning Acoustic Microscopy | Non-destructive imaging of delamination and voids. |
| PBO | Polybenzoxazole | Polymer dielectric used in RDL (like polyimide). |
| EOS | Electrical Overstress | Damage from overvoltage or overcurrent beyond ESD events. |
| BGA | Ball Grid Array | FC-BGA = flip-chip BGA. |
| eWLB | embedded Wafer-Level Ball-grid-array | Fan-out package with low RF loss. |
| AoP | Antenna-on-Package | |
| LoP | Launch-on-Package | RF launched from package into waveguide / antenna. |
| GCPW | Grounded Coplanar Waveguide | PCB transmission line at the ball launch. |
| SIW | Substrate-Integrated Waveguide | Waveguide formed with via fences in the PCB. |
| FR4 | Flame-Retardant epoxy-glass laminate | Standard low-cost PCB material. |
| ENEPIG | Electroless Nickel, Electroless Palladium, Immersion Gold | PCB surface finish. |
| ImAg | Immersion Silver | PCB surface finish. |
| HASL | Hot-Air Solder Leveling | Surface finish; too rough/uneven for 77 GHz. |
| PBT | Polybutylene terephthalate (PC = polycarbonate) | Radome plastics. |
| HFSS | High-Frequency Structure Simulator (Ansys) | 3D EM simulator (CST = Dassault's equivalent). |