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Power management: supplies, LDOs and UV/OV monitors
SupplySafetyA radar SoC runs a 20 GHz VCO that turns microvolts of supply noise into FM, PAs that switch hundreds of mA every chirp, precise IF/ADC circuits and a large digital core, all from a 12 V car battery through an external PMIC. The on-chip power system has three jobs: regulate each domain cleanly (LDOs and the bandgap reference), sequence start-up and shutdown safely, and monitor every rail so that any under- or over-voltage is caught before it corrupts radar data (an ISO 26262 safety mechanism). The overview is in the signal-chain power section; this page goes into the circuits.
LDO regulator
VOUT = V_ref · (1 + R1 / R2)
Dropout: V_DO = I_load · R_on(pass) → need VIN − VOUT ≥ V_DO (+ margin at slow corner, hot)
Dissipation: P = (VIN − VOUT) · I_load Efficiency ≈ VOUT / VIN
Load regulation: ΔVOUT / ΔI_load Line regulation: ΔVOUT / ΔVIN
Loop: dominant pole at the output (1 / R_out·C_out) for PMOS + external C;
ESR zero (1 / ESR·C_out) helps phase margin → keep ESR in its allowed range
| Topology | How it works | Strength | Weakness | Radar use |
|---|---|---|---|---|
| PMOS pass + external C_out | Error amp drives the PMOS gate; dominant pole at the output | Low dropout, simple, very low noise at low frequency | PSRR falls above the loop bandwidth (≈ 0.1–1 MHz); needs a µF-class pin capacitor; stability depends on ESR | IO, bandgap/aux, analog with an external cap |
| NMOS source follower (cap-less) | Pass device as a follower; dominant pole at the gate; small on-chip C | Fast load transients, good high-frequency PSRR, no pin | Needs gate drive above VIN (charge pump) or more headroom | PA/RF rails with Tx load steps, VCO |
| Cascaded (pre-regulator + LDO) | Two regulators in series | PSRR adds (> 80 dB) | More dropout (needs 1.8 V in for a ≈ 1.2 V out) | VCO, reference |
| Digital LDO | Array of switched pass devices controlled by a comparator loop | Works at very low headroom, scales with the process | Ripple and limit cycles; poor PSRR | Digital core, SRAM retention |
Bandgap reference
Every LDO and every UV/OV threshold is only as accurate as its reference. A bandgap adds a voltage that falls with temperature (a diode's V_BE, about −2 mV/°C) to one that rises with it (a scaled ΔV_BE of two diodes at different current densities, proportional to absolute temperature) so the sum is nearly temperature-independent:
V_BG = V_BE + K · (kT/q) · ln(N) ≈ 1.2 V (CTAT + PTAT)
Accuracy after trim: ≈ ±0.5 % Temperature drift: ≈ 10–30 ppm/°C
Low-voltage variants output a scaled current or a sub-1 V reference
- Trim: the bandgap is trimmed first at wafer test (eFuse), because every later trim and measurement depends on it (see the test flow).
- Two independent bandgaps: one for regulation, one for the monitors. If a single bandgap drifted, the LDO output and its UV/OV threshold would drift together and the fault would be invisible (a common-cause failure).
- Start-up circuit: a bandgap has a stable zero-current state; a start-up circuit forces it out of that state at power-up, and is itself checked by the POR.
UV / OV monitors and other protections
| Monitor / protection | What it detects | Typical setting | Action |
|---|---|---|---|
| UV (under-voltage) | Rail below its window: brown-out, LDO dropout, overload | V_nom − 5…10 %, accuracy ±1–2 %, hysteresis 1–2 %, deglitch 1–10 µs | Fault flag; for core rails, reset |
| OV (over-voltage) | Rail above its window: regulator failure, PMIC fault, short to a higher rail | V_nom + 5…10 % | Fault flag; switch the rail or the chip off to protect oxides |
| POR / BOR | Supply too low to guarantee logic state at power-up (POR) or during operation (brown-out) | Threshold below the UV level; delay 0.1–10 ms after all rails are valid | Hold nRESET until everything is valid |
| Over-current limit | Short or overload on an LDO output | ≈ 1.5–2 × max load; fold-back | Limit current, flag, avoid thermal damage |
| Over-temperature | Die temperature too high | Warning ≈ 140 °C, shutdown ≈ 165–175 °C with hysteresis | Reduce Tx duty, then shut down |
| Monitor self-test | A monitor that can no longer trip (latent fault) | At start-up, force each threshold past the rail and check the flag | ISO 26262 latent-fault coverage |
Power-up sequencing
- Why the order matters: an input driven while its own supply is off can back-power the rail through ESD diodes; a core that starts before its IO can drive pins to undefined states; RF blocks enabled before the PLL locks radiate off-frequency.
- Inrush: charging large decoupling capacitors at start-up draws a current spike; soft-start ramps each LDO to keep inrush and supply droop within the PMIC's limits.
Issues and failure modes
| Issue | Symptom in the radar | Typical cause | Fix / how it's caught |
|---|---|---|---|
| LDO oscillation | Supply ringing, spurs, random resets | Output capacitor or ESR outside the stable range; light-load pole moves | Stability analysis over load, C and ESR; board rules for C_out |
| Dropout at a corner | VOUT sags under load, UV trips when hot or at low VIN | Pass device too small for slow corner / hot; PMIC rail at its low limit | Size pass device at SS/hot; test at minimum VIN and hot |
| Poor PSRR at buck frequency | Spurs in the IF spectrum, VCO FM sidebands | PSRR dip near the buck switching frequency | NMOS or cascaded LDO, buck frequency planning, loopback spur check |
| Load-transient droop | Tx-to-Tx phase error in TDM MIMO | PA current step faster than the LDO loop | Faster loop, more local decoupling, idle time before sampling |
| False UV/OV trips | Unexpected resets or fault flags | Deglitch too short, thresholds too tight, supply noise | Correct deglitch and hysteresis; check noise at the monitor input |
| Missed fault (latent) | Radar keeps running on a bad rail | Comparator or reference failed silently; shared reference | Independent BG2, start-up self-test of each monitor |
| Back-powering | Chip partly powered through IO pins, won't reset | Signals applied before supplies; ESD diode current paths | Sequencing rules, fail-safe IO, POR on every domain |
| Reference drift | All rails shift together, trims out of range | Bandgap trim error, package stress shift after assembly | Trim at wafer, re-check at final test, stress-aware layout |
| Thermal overload | Over-temperature shutdowns in a hot bumper | LDO dissipation (VIN − VOUT)·I too high | Lower headroom rails, spread dissipation, derate Tx duty |
PCM / WAT items that matter for power circuits
| PCM / WAT item | Circuit | Effect |
|---|---|---|
| PMOS / NMOS Vt, Idsat | Pass device, error amplifier | Dropout and headroom at the slow corner; error-amp gain and bandwidth |
| Bipolar (parasitic PNP) V_BE and its spread | Bandgap | Untrimmed reference value and temperature coefficient; trim range needed |
| Resistor sheet resistance and matching | Feedback divider, threshold ladder, bandgap resistors | VOUT and UV/OV threshold accuracy (ratios matter, not absolute values) |
| MIM / MOM capacitance | Compensation, cap-less LDO output | Loop stability and transient response |
| Ioff, junction leakage | All, especially at hot | Quiescent current, standby power, reference error from leakage |
| Gate-oxide Vbd, BVdss | Pass devices, OV protection clamps | How much over-voltage the chip survives before OV shutdown acts |
Production test of the power system
- Power-rail short check before any supply ramps (see open/short).
- Bandgap trim against a precision tester voltage; then each LDO VOUT trim; burn eFuse and re-measure.
- Line and load regulation: step VIN and the load (on-chip load switches or tester PMU), measure VOUT.
- UV/OV threshold test: sweep each rail slowly with the tester supply and record the trip and release points (threshold and hysteresis); also verifies the deglitch time with short pulses.
- POR threshold and delay, over-current limit and over-temperature flag (forced via test mode).
- Quiescent current (IDDQ-like) of each LDO and the standby current; outliers go to PAT.
- Monitor self-test exercised the same way the firmware runs it at key-on.
LDO and UV/OV calculator
VOUT
–
Headroom above dropout
Dissipation / efficiency
UV / OV trip points
Divider current (Iq share)
01
Glossary of abbreviations
Abbreviations are underlined with dots the first time they appear in each section. Hover to see the meaning; click to jump here. Use Search (Ctrl+K) to find an abbreviation anywhere on the page.
Radar system & ADAS
| Abbr. | Stands for | Note |
|---|---|---|
| FCW | Forward Collision Warning | Warns of an imminent frontal collision; stage before AEB. |
| FCTA | Front Cross-Traffic Alert | Front corner-radar function at junctions and driveways. |
| RCTB | Rear Cross-Traffic Braking | Brakes automatically when RCTA detects cross traffic while reversing. |
| DOW | Door-Opening Warning | Warns before a door is opened into an approaching cyclist or car. |
| VRU | Vulnerable Road User | Pedestrians, cyclists and motorcyclists. |
| TTC | Time To Collision | Range divided by closing speed; triggers warnings and braking. |
| LRR | Long-Range Radar | Front radar, ≈ 200–300 m, narrow field of view. |
| MRR | Mid-Range Radar | ≈ 80–160 m, ±40–60° field of view. |
| SRR | Short-Range Radar | Corner radar, ≈ 30–80 m, ±75–90° field of view. |
| NCAP | New Car Assessment Programme | Consumer safety ratings (Euro NCAP, C-NCAP, IIHS …). |
| GSR | General Safety Regulation (EU) 2019/2144 | Makes AEB and other assistance functions mandatory in the EU. |
| CPD | Child Presence Detection | In-cabin sensing (often 60 GHz radar) that detects a child left in the car. |
| ACC | Adaptive Cruise Control | Keeps distance to the car ahead; uses long-range front radar. |
| ADAS | Advanced Driver-Assistance Systems | The vehicle functions the radar serves. |
| AEB | Autonomous Emergency Braking | Brakes automatically when a collision is imminent. |
| BSD | Blind-Spot Detection | Corner-radar function. |
| LCA | Lane-Change Assist | Corner-radar function that warns of fast approaching vehicles. |
| RCTA | Rear Cross-Traffic Alert | Rear corner-radar function when reversing. |
| L2 | SAE automation Level 2 (L3 = Level 3) | Partial (L2) and conditional (L3) driving automation. |
| FMCW | Frequency-Modulated Continuous Wave | A linear chirp; range comes from the beat frequency f_b = S·2R/c. |
| FoV | Field of View | Angular coverage in azimuth and elevation. |
| RCS | Radar Cross Section | Target reflectivity in dBsm (car ≈ 10, pedestrian ≈ −10…0). |
| dBsm | Decibels relative to 1 m² | Unit of RCS. |
| EIRP | Effective Isotropic Radiated Power | Tx power + antenna gain; limited by regulations. |
| MIMO | Multiple-Input Multiple-Output | N_tx × N_rx channels form a larger virtual array. |
| TDM | Time-Division Multiplexing | One Tx per chirp; v_max falls by a factor of N_tx. |
| BPM | Binary Phase Modulation | 0/180° codes across chirps separate the Tx signals. |
| DDMA | Doppler-Division Multiple Access | Each Tx gets a slow-time phase ramp and separates in Doppler. |
| DoA | Direction of Arrival | Angle estimation over the virtual array. |
| DBF | Digital Beamforming | FFT or matched steering over array channels. |
| CFAR | Constant False Alarm Rate | Adaptive detection threshold (CA = cell-averaging, OS = ordered-statistic). |
| FFT | Fast Fourier Transform | Range, Doppler and angle FFTs build the radar cube. |
| SNR | Signal-to-Noise Ratio | |
| MUSIC | MUltiple SIgnal Classification | Subspace super-resolution DoA algorithm. |
| ESPRIT | Estimation of Signal Parameters via Rotational Invariance Techniques | Super-resolution DoA algorithm. |
| IAA | Iterative Adaptive Approach | Super-resolution spectral / DoA estimator. |
| DBSCAN | Density-Based Spatial Clustering of Applications with Noise | Groups detections into objects. |
| EKF | Extended Kalman Filter | Nonlinear tracking filter. |
| UKF | Unscented Kalman Filter | Nonlinear tracking filter using sigma points. |
| IMM | Interacting Multiple Model | Tracker that mixes several motion models. |
| HWA | Hardware Accelerator | On-chip FFT / radar processing engine. |
| RTS | Radar Target Simulator | Echo generator for HIL and EOL testing. |
| HIL | Hardware-in-the-Loop | Testing the real sensor against simulated scenarios. |
| EOL | End-of-Line | Final production test of a module or vehicle. |
RF & analog front end
| Abbr. | Stands for | Note |
|---|---|---|
| HPBW | Half-Power Beamwidth | Angle between the −3 dB points of an antenna or array beam. |
| PDN | Power Delivery Network | Regulators, planes, decoupling and package paths that supply the chip. |
| PI | Power Integrity | Keeping supply voltage within limits under load steps and noise. |
| EMI | Electromagnetic Interference | Unwanted emission or pick-up of electromagnetic energy. |
| BCI | Bulk Current Injection | Immunity test (ISO 11452-4) that injects RF current into a cable harness. |
| TIM | Thermal Interface Material | Gap pad or paste between board or package and the heat sink. |
| RF | Radio Frequency | Here the 76–81 GHz signal. |
| LO | Local Oscillator | The chirp signal that drives the Tx and the Rx mixers. |
| IF | Intermediate Frequency | The beat / baseband signal after the mixer, DC–20 MHz. |
| PA | Power Amplifier | Tx output stage, 12–14 dBm. |
| LNA | Low-Noise Amplifier | First Rx stage; sets most of the NF. |
| NF | Noise Figure | Noise the receiver adds, in dB. |
| VGA | Variable-Gain Amplifier | Programmable-gain stage (IF), or signed VGAs in the phase rotator. |
| TIA | Transimpedance Amplifier | Current-to-voltage stage after a passive mixer. |
| HPF | High-Pass Filter | In IF: removes leakage and DC, and equalises R⁻⁴. |
| LPF | Low-Pass Filter | |
| AAF | Anti-Aliasing Filter | Low-pass filter in front of the ADC. |
| PPF | Polyphase Filter | RC-CR network that generates I/Q. |
| I/Q | In-phase / Quadrature | Two copies of a signal 90° apart. |
| IRR | Image Rejection Ratio | How well an I/Q path suppresses the mirror frequency. |
| SSB | Single Sideband | A frequency shift in one direction only, e.g. the loopback offset. |
| BPSK | Binary Phase-Shift Keying | 0/180° switching; produces ±f_m sidebands. |
| VM | Vector Modulator | I/Q-weighted phase rotator. |
| RTPS | Reflection-Type Phase Shifter | Hybrid coupler terminated by tunable loads. |
| P1dB | 1 dB compression point | Input (or output) level where gain drops by 1 dB. |
| IIP3 | Input third-order intercept point | Linearity figure; cascades with the gain before each stage. |
| PAE | Power-Added Efficiency | (P_out − P_in) / P_DC of a PA. |
| Psat | Saturated output power | Maximum output power of a PA. |
| DSB | Double Sideband | Noise figure counting both sidebands (typical for zero-IF mixers). |
| PGA | Programmable-Gain Amplifier | IF VGA with digitally set gain steps. |
| AGC | Automatic Gain Control | Loop that sets the VGA gain from the signal level. |
| HD2 | 2nd-order Harmonic Distortion (HD3 = 3rd) | Harmonics show up as ghost targets at 2×/3× range. |
| AM/PM | Amplitude-to-phase conversion | Phase change caused by amplitude or supply changes. |
| RL | Return Loss | Match quality, in dB. |
| Cpl | Coupler (directional coupler) | Taps a small, known fraction (−15…−20 dB) of a signal for detection or loopback. |
| PD | Power Detector | Diode or square-law RF-to-DC converter. |
| APC | Automatic Power Control | Closed loop from the power detector to the VGA/PA gain code. |
| DPD | Digital Predistortion | Wideband PA linearisation used in comms; radar uses static gain/phase LUTs instead. |
| VSWR | Voltage Standing-Wave Ratio | Mismatch at the antenna/load; changes the delivered power. |
| CW | Continuous Wave | An unmodulated single-frequency tone. |
| ENR | Excess Noise Ratio | Calibrated output level of a noise source. |
| SiGe | Silicon-Germanium (BiCMOS) | Bipolar-plus-CMOS process used for earlier radar chips. |
| CMOS | Complementary Metal-Oxide-Semiconductor | RFCMOS = CMOS process with RF / mmWave capability. |
| RFCMOS | RF-capable CMOS | Today's single-chip radar process (e.g. 45/40/28/22 nm). |
| NMOS | N-channel MOS transistor (PMOS = P-channel) | |
| PTAT | Proportional To Absolute Temperature | Voltage or current used by temperature sensors. |
| BG | Bandgap reference | Temperature-stable voltage reference (BG1/BG2 = two independent ones). |
| PVT | Process, Voltage, Temperature | Variation corners a design must cover. |
LO, clock & synthesis
| Abbr. | Stands for | Note |
|---|---|---|
| PLL | Phase-Locked Loop | Locks the VCO to the crystal and generates the ramp. |
| ADPLL | All-Digital PLL | PLL with a TDC and a digital loop filter. |
| VCO | Voltage-Controlled Oscillator | ≈ 19–20.25 GHz, multiplied ×4 to 77 GHz. |
| PFD | Phase-Frequency Detector | Compares the divided VCO with the reference. |
| CP | Charge Pump; also Chip Probe | In a PLL: converts PFD pulses into loop-filter current. In test flows: wafer-level probe test. |
| TDC | Time-to-Digital Converter | Digital phase detector of an ADPLL. |
| XTAL | Crystal (reference oscillator) | 40/50 MHz reference for PLL, ADC and digital. |
| DDS | Direct Digital Synthesizer | Digitally generated tone (IF test tone). |
| Kvco | VCO gain | Tuning sensitivity in MHz/V; varies per band. |
| AFC | Automatic Frequency Calibration (band calibration) | Picks the VCO capacitor-bank band before the PLL closes. |
| MMD | Multi-Modulus Divider | Programmable divider in the PLL feedback, dithered by the ΣΔ modulator. |
| CML | Current-Mode Logic | Fast differential logic used for the first divider (prescaler) stages at 20 GHz. |
Data conversion & digital
| Abbr. | Stands for | Note |
|---|---|---|
| SNM | Static Noise Margin | Noise an SRAM cell tolerates before flipping; read SNM is the critical one. |
| SEU | Single-Event Upset | Bit flip caused by a particle strike (soft error). |
| SER | Soft-Error Rate | Rate of radiation-induced bit flips, in FIT per Mbit. |
| MBU | Multi-Bit Upset | One particle flips several neighbouring cells. |
| RDF | Random Dopant Fluctuation | Random number of dopant atoms in a small channel; main cause of Vth mismatch. |
| LER | Line-Edge Roughness | Rough gate edges that add Vth variation in small devices. |
| NPSF | Neighbourhood Pattern-Sensitive Fault | Memory cell fails only for certain data in its neighbours. |
| SEC-DED | Single-Error Correction, Double-Error Detection | ECC code used on memory words (e.g. 64 + 8 bits). |
| ROM | Read-Only Memory | Mask-programmed memory for boot code and tables. |
| DRF | Data-Retention Fault | Memory cell loses its value after a pause. |
| WL | Word Line | Row select line of a memory array. |
| BL | Bit Line | Column data line of a memory array (BL and its complement BLB). |
| OSR | Oversampling Ratio | fs / (2·BW) of a ΣΔ ADC; each doubling adds (2L+1)·3 dB of SQNR. |
| NTF | Noise Transfer Function | How a ΣΔ loop shapes quantisation noise out of the signal band. |
| SNDR | Signal-to-Noise-and-Distortion Ratio | ENOB = (SNDR − 1.76) / 6.02. |
| GBW | Gain-Bandwidth product | Op-amp figure of merit; sets filter and PGA accuracy at IF. |
| CMRR | Common-Mode Rejection Ratio | How well a differential circuit rejects signals common to both inputs. |
| CSI-2 | MIPI Camera Serial Interface 2 | High-speed serial link used for raw radar data. |
| TSN | Time-Sensitive Networking | Deterministic automotive Ethernet (IEEE 802.1). |
| ADC | Analog-to-Digital Converter | Main Rx ADCs (ΣΔ) and the aux SAR ADC. |
| DAC | Digital-to-Analog Converter | Rotator I/Q weights, bias, trim, test-tone generation. |
| SAR | Successive-Approximation Register ADC | Slow, precise ADC used for monitoring. |
| CT | Continuous-Time (CT-ΣΔ) | Sigma-delta ADC with a continuous-time loop filter. |
| ENOB | Effective Number of Bits | |
| SFDR | Spurious-Free Dynamic Range | Tone relative to the largest spur. |
| THD | Total Harmonic Distortion | |
| DR | Dynamic Range | |
| INL | Integral Nonlinearity | Deviation from the ideal transfer line. |
| DNL | Differential Nonlinearity | Deviation of each step from 1 LSB. |
| LSB | Least Significant Bit (MSB = most significant) | |
| DFE | Digital Front End | Decimation, DC and I/Q correction, interference handling. |
| CIC | Cascaded Integrator-Comb | Multiplier-free decimation filter. |
| FIR | Finite Impulse Response filter | |
| DSP | Digital Signal Processor | |
| MCU | Microcontroller Unit | |
| CPU | Central Processing Unit | E.g. the RF control CPU that runs chirps and monitors. |
| SoC | System-on-Chip | |
| ECU | Electronic Control Unit | Vehicle computer that receives radar data. |
| SRAM | Static RAM (RAM = random-access memory) | |
| ECC | Error-Correcting Code | Memory protection for functional safety. |
| DMA | Direct Memory Access | |
| LUT | Look-Up Table | E.g. phase-code → (I, Q) DAC codes, Tx power vs. temperature. |
| FW | Firmware (SW = software) | |
| OTP | One-Time Programmable memory | Holds trims and IDs, like eFuse. |
| SPI | Serial Peripheral Interface | Configuration / test bus from host or ATE. |
| CAN | Controller Area Network (CAN-FD = Flexible Data-rate) | Vehicle bus for object lists. |
| ETH | Ethernet (100/1000BASE-T1) | Automotive single-pair Ethernet. |
| CSI | Camera Serial Interface (MIPI CSI-2) | Streams raw radar data to a central SoC. |
| LVDS | Low-Voltage Differential Signaling | Raw-data debug / streaming interface. |
| GPIO | General-Purpose Input/Output | |
| IO | Input/Output |
Power
| Abbr. | Stands for | Note |
|---|---|---|
| LDO | Low-Dropout regulator | Linear regulator; one per noise-sensitive domain. |
| PMIC | Power-Management IC | External bucks, supervisors and watchdog. |
| PSRR | Power-Supply Rejection Ratio | How much supply ripple an LDO (or circuit) blocks. |
| UV | Under-Voltage (OV = Over-Voltage) | Supply monitors, a safety mechanism. |
| OV | Over-Voltage | Rail above its window; OV monitor protects gate oxides. |
| POR | Power-On Reset | Holds the chip in reset until all rails are valid. |
| BOR | Brown-Out Reset | Resets when a supply sags during operation. |
| ESR | Equivalent Series Resistance | Of the LDO output capacitor; its zero affects loop stability. |
| OCP | Over-Current Protection | Current limit on a regulator output. |
| Iq | Quiescent current | Current a regulator draws for itself with no load. |
| DLDO | Digital LDO | Switched pass-device array regulated by a comparator loop. |
| GND | Ground |
Test & production
| Abbr. | Stands for | Note |
|---|---|---|
| EVB | Evaluation Board | Board that carries the chip on the bench with supplies, clock, interfaces and RF transitions. |
| SMU | Source-Measure Unit | Precision instrument that forces voltage or current and measures the other. |
| OTA | Over The Air | Measurement through antennas in a chamber instead of a cable or waveguide. |
| GSG | Ground-Signal-Ground probe | RF wafer probe with a signal tip between two ground tips. |
| LRRM | Line-Reflect-Reflect-Match calibration | On-wafer VNA calibration method for mmWave probes. |
| SCPI | Standard Commands for Programmable Instruments | Text command set used to automate instruments. |
| UPH | Units Per Hour | Test throughput of a tester and handler. |
| eFuse | Electrically programmable fuse | Silicided poly link blown by current; stores trim, ID and repair bits. |
| MTP | Multiple-Time Programmable memory | Small NVM that can be rewritten a few times. |
| NVM | Non-Volatile Memory | Keeps data without power: eFuse, OTP, MTP, flash. |
| VPP | Programming supply voltage | Supply used only to program fuses or OTP. |
| CRC | Cyclic Redundancy Check | Checksum that detects corrupted data, e.g. trim words at boot. |
| RMA | Return Material Authorization | A customer return, analysed through the 8D process. |
| 8D | Eight Disciplines | Structured problem solving: team, describe, contain, root cause, correct, verify, prevent, close. |
| MSA | Measurement System Analysis | Proves a measurement is precise and accurate enough (Gage R&R, bias, stability). |
| GRR | Gage Repeatability and Reproducibility | %GRR < 10 % of tolerance is good. |
| BIST | Built-In Self-Test | On-chip stimulus + measurement; result is pass/fail or a value checked against a limit. |
| BISM | Built-In Self-Measurement | Same on-chip hardware, but the result is a calibrated value (dB, °, MHz) used for trim, calibration and trend. |
| DFT | Design for Test | |
| ATE | Automatic Test Equipment | Production tester. |
| ATPG | Automatic Test Pattern Generation | Scan patterns for digital logic. |
| IDDQ | Quiescent supply-current test | Detects leakage defects. |
| PMU | Parametric Measurement Unit | ATE DC source/measure channel. |
| Cres | Contact resistance | Probe or socket contact resistance; measured with the Kelvin or two-current method. |
| FIMV | Force Current, Measure Voltage | PMU mode used for open/short (diode) tests. |
| FVMI | Force Voltage, Measure Current | PMU mode used for leakage and power-short tests. |
| IIL | Input leakage current, input Low (IIH = input High) | Leakage limit per IO pin, typically |I| < 1 µA. |
| IIH | Input leakage current, input High | |
| ESD | Electrostatic Discharge | Pad protection diodes / clamps; the diode method uses them for continuity. |
| VDD | Positive supply rail (VSS = ground / negative rail) | |
| VSS | Ground / negative supply rail | |
| DCR | DC Resistance | E.g. of an RF shunt inductor, 0.5–3 Ω. |
| Hi-Z | High impedance (Z) | Output driver switched off; the pin floats. |
| OE | Output Enable | Control that switches an output between driving and Hi-Z. |
| IOZ | Off-state output leakage (IOZH at VDDIO, IOZL at 0 V) | Measured on a pin in Hi-Z; typically |I| < 1–10 µA. |
| VOH | Output High voltage threshold (VOL = Output Low) | Tester comparator levels that decide 1 / Z / 0. |
| VOL | Output Low voltage threshold | |
| HIGHZ | IEEE 1149.1 instruction that puts all outputs in Hi-Z | |
| EXTEST | IEEE 1149.1 external test instruction | Boundary cells drive and sample the pins; used for interconnect and walking-Z tests. |
| RPCT | Reduced Pin-Count Testing | Testing through JTAG / a few pins, so more sites fit on one tester. |
| BICS | Built-In Current Sensor | On-chip current monitor for IDDQ per power domain. |
| SPC | Statistical Process Control | |
| VNA | Vector Network Analyzer | Lab instrument for S-parameters. |
| AWG | Arbitrary Waveform Generator | |
| DMM | Digital Multimeter | |
| GPIB | General-Purpose Interface Bus | Instrument control bus (like LAN). |
Safety, standards & regulation
| Abbr. | Stands for | Note |
|---|---|---|
| PMHF | Probabilistic Metric for random Hardware Failures | ISO 26262 residual failure rate; < 100 FIT for ASIL B/C, < 10 FIT for D. |
| SEooC | Safety Element out of Context | A part developed to ISO 26262 against assumed system requirements. |
| FMEA | Failure Mode and Effects Analysis | Qualitative analysis of failure modes; FMEDA adds rates and diagnostic coverage. |
| FIT | Failures In Time | Failures per 10⁹ device-hours. |
| MTTF | Mean Time To Failure | |
| RED | Radio Equipment Directive (EU 2014/53/EU) | EU conformity framework for radio transmitters, including radar. |
| ASIL | Automotive Safety Integrity Level | ISO 26262 risk class A–D; radar typically ASIL-B. |
| ISO | ISO 26262 / ISO/SAE 21434 / ISO 11452 | Functional safety / cybersecurity / EMC immunity. |
| FTTI | Fault-Tolerant Time Interval | Time from fault to hazard; monitors must react within it. |
| FMEDA | Failure Modes, Effects and Diagnostic Analysis | |
| SPFM | Single-Point Fault Metric | ISO 26262 coverage metric. |
| LFM | Latent Fault Metric | ISO 26262 coverage metric. |
| AEC | Automotive Electronics Council (AEC-Q100 / Q200) | Qualification of ICs / passives. |
| ETSI | European Telecommunications Standards Institute | EN 301 091 / EN 303 396 radar standards. |
| FCC | Federal Communications Commission | US rules, Part 95M for 76–81 GHz. |
| EMC | Electromagnetic Compatibility | |
| CISPR | Comité International Spécial des Perturbations Radioélectriques | CISPR 25: vehicle-component emissions. |
| OOB | Out-of-Band (emission) |
Digital DFT, stress & reliability
| Abbr. | Stands for | Note |
|---|---|---|
| UHST | Unbiased Highly Accelerated Stress Test | HAST without bias, 130 °C / 85 % RH; alternative to autoclave. |
| PTC | Power Temperature Cycling | Temperature cycling with the device powered on and off. |
| EDR | Endurance and Data Retention | Qualification of non-volatile memory (AEC-Q100-005). |
| DPA | Destructive Physical Analysis | Opening and sectioning parts to inspect their construction and damage. |
| SEM | Scanning Electron Microscope | High-magnification imaging of cross-sections and surfaces. |
| EDX | Energy-Dispersive X-ray spectroscopy | Element analysis in the SEM: corrosion, contamination, IMC phases. |
| FIB | Focused Ion Beam | Precise local cutting and imaging; also used for circuit edits. |
| LTPD | Lot Tolerance Percent Defective | Defect rate a sampling plan rejects with given confidence; 0 / 231 ≈ 1 % at 90 %. |
| PC | Preconditioning | Bake, moisture soak and reflow before environmental stress (JESD22-A113). |
| BLR | Board-Level Reliability | Reliability of the package soldered on a PCB (temperature cycling, drop, vibration). |
| SAC | Tin-Silver-Copper solder | Lead-free solder alloy (e.g. SAC305) used for balls. |
| PPAP | Production Part Approval Process | Automotive approval package, includes the qualification report. |
| DRC | Design Rule Check | Verifies layout against foundry manufacturing rules. |
| LVS | Layout Versus Schematic | Verifies that the layout matches the schematic netlist. |
| PEX | Parasitic Extraction | Extracts resistance, capacitance (and inductance) of the layout for post-layout simulation. |
| AMS | Analog / Mixed-Signal simulation | Simulation that combines transistor-level analog with digital models. |
| ECO | Engineering Change Order | Late design fix; a metal-only ECO changes only upper masks. |
| SCR | Silicon-Controlled Rectifier | Thyristor; used as a compact ESD clamp, and the parasitic structure behind latch-up. |
| GGNMOS | Grounded-Gate NMOS | ESD clamp that works by parasitic-bipolar snapback. |
| SE | Scan Enable | Selects shift (SE = 1) or functional capture (SE = 0) in scan flops. |
| SAF | Stuck-At Fault | Node permanently 0 or 1. |
| TDF | Transition Delay Fault | Node slow to rise or fall; needs at-speed test. |
| STA | Static Timing Analysis | Finds the longest paths for timing-aware ATPG. |
| OCV | On-Chip Variation | Timing derates in STA that account for local (mismatch) variation across the die. |
| OCC | On-Chip Clock Controller | Gates exact launch/capture pulses from the PLL for at-speed test. |
| LOC | Launch-On-Capture | At-speed scheme; also called broadside. |
| LOS | Launch-On-Shift | At-speed scheme; SE must switch at speed. |
| EDT | Embedded Deterministic Test | Scan compression (decompressor + compactor). |
| LFSR | Linear-Feedback Shift Register | Pseudo-random sequence generator. |
| PRPG | Pseudo-Random Pattern Generator | LFSR that feeds the scan chains in LBIST. |
| MISR | Multiple-Input Signature Register | Compresses responses into one signature. |
| STUMPS | Self-Test Using MISR and Parallel Shift-register sequence generator | Standard LBIST architecture. |
| LBIST | Logic BIST | On-chip random-pattern scan test; used at key-on. |
| MBIST | Memory BIST | On-chip March-algorithm test of SRAMs. |
| BIRA | Built-In Redundancy Analysis | Computes which spare rows/columns repair a memory. |
| BISR | Built-In Self-Repair | Loads the repair from eFuse at boot. |
| IR | IR drop | Supply voltage drop (current × resistance), high during scan shift. |
| JTAG | Joint Test Action Group (IEEE 1149.1) | Boundary scan and test access port. |
| TAP | Test Access Port | JTAG pins TCK, TMS, TDI, TDO, TRST. |
| BSDL | Boundary Scan Description Language | Describes a chip's JTAG boundary-scan cells. |
| IJTAG | Internal JTAG (IEEE 1687) | Network for accessing on-chip instruments. |
| MUX | Multiplexer | Selects one of N inputs; in test, routes sub-block nodes to shared instruments. |
| ATB | Analog Test Bus | Chip-wide wire pair (force + sense) that test muxes connect sub-block nodes to. |
| TG | Transmission Gate | Parallel NMOS + PMOS switch; passes the full voltage range. |
| SPDT | Single-Pole Double-Throw switch | One input to one of two outputs (SP4T = one of four). |
| BBM | Break-Before-Make | Switching order that opens the old path before closing the new one. |
| ICL | Instrument Connectivity Language (PDL = Procedural Description Language) | IJTAG description files. |
| ECID | Electronic Chip ID | Unique per-die ID for traceability. |
| HVST | High-Voltage Stress Test | Short over-voltage on the core rail to activate latent oxide defects. |
| VLV | Very-Low-Voltage test | Test below nominal V to expose resistive defects. |
| Vmin | Minimum operating voltage | The pass/fail edge in a shmoo; an outlier Vmin flags a defect. |
| PAT | Part Average Testing (AEC-Q001) | Outlier limits at robust μ ± 6σ. |
| DPAT | Dynamic Part Average Testing | PAT limits recalculated per lot or wafer. |
| GDBN | Good Die in Bad Neighbourhood | Wafer-map screen that rejects dies in defect clusters. |
| NNR | Nearest-Neighbour Residual | Compares a die's parameter with its wafer neighbours. |
| DPPM | Defective Parts Per Million | Shipped-quality metric; automotive target ≪ 1. |
| FT | Final Test | Package-level production test. |
| SLT | System-Level Test | Functional test by booting the application. |
| PCM | Process Control Monitor | Test structures in the scribe lines, measured by the fab (see WAT). |
| WAT | Wafer Acceptance Test | Fab's electrical test of PCM structures before shipping wafers. |
| OSAT | Outsourced Semiconductor Assembly and Test | Company that packages and tests the dies. |
| QA | Quality Assurance | Sample-based outgoing inspection and audits. |
| Cp | Process capability (Cp) | (USL − LSL) / 6σ: spec width vs process spread. |
| Cpk | Process capability index | min(USL − μ, μ − LSL) / 3σ; automotive often ≥ 1.33, critical ≥ 1.67. |
| USL | Upper Spec Limit (LSL = Lower Spec Limit) | Design limits; outside them the part is out of spec. |
| LSL | Lower Spec Limit | |
| UCL | Upper Control Limit (LCL = Lower Control Limit) | Process limits from history, usually mean ± 3σ. |
| LCL | Lower Control Limit | |
| OCAP | Out-of-Control Action Plan | Documented steps when an SPC rule fires. |
| MRB | Material Review Board | Decides what happens to held material: release, rework, scrap or deviation. |
| MIM | Metal-Insulator-Metal capacitor (MOM = Metal-Oxide-Metal) | Precision on-chip capacitors. |
| MOM | Metal-Oxide-Metal (finger) capacitor | |
| BSIM | Berkeley Short-channel IGFET Model | Industry-standard compact transistor model family used in design kits. |
| Vt | Threshold voltage | Gate voltage where the channel turns on; Vt_lin at low Vds, Vt_sat at VDD. |
| Idsat | Saturation drain current | Id at Vgs = Vds = VDD, per µm of width; transistor strength. |
| Ioff | Off-state leakage current | Id at Vgs = 0, Vds = VDD. |
| DIBL | Drain-Induced Barrier Lowering | Vt drop per volt of Vds in short-channel devices. |
| SS | Subthreshold swing (also SS = slow-slow process corner) | mV of Vgs per decade of Id below Vt; ≈ 60 mV/dec ideal at room temperature. |
| TT | Typical-typical process corner | FF = fast-fast; FS / SF = skewed NMOS / PMOS corners. |
| FF | Fast-fast process corner | |
| gm | Transconductance | ∂Id/∂Vgs; the transistor's gain. |
| gds | Output conductance | ∂Id/∂Vds; limits voltage gain (intrinsic gain = gm/gds). |
| Cox | Gate-oxide capacitance per area | εox / Tox. |
| Tox | Gate-oxide thickness | Measured with C-V structures in WAT. |
| fT | Transit (unity current-gain) frequency | ≈ gm / 2π(Cgs + Cgd). |
| fmax | Maximum oscillation (unity power-gain) frequency | Needs ≈ 3–4× the operating frequency for useful gain. |
| Vbd | Gate-oxide breakdown voltage | Voltage where oxide current jumps past compliance in a V-ramp test. |
| BV | Breakdown Voltage | BVdss = drain-source (gate off), BVj = junction. |
| BVdss | Drain-source breakdown voltage | Transistor off-state breakdown; limits PA drain swing. |
| BVj | Junction breakdown voltage | Reverse breakdown of N+/P-well or P+/N-well diodes. |
| TLP | Transmission-Line Pulse | ESD device characterisation with short, high-current pulses. |
| QBD | Charge to breakdown | Total charge an oxide passes before breaking down (reliability). |
| IMD | Inter-Metal Dielectric | Insulator between metal lines/layers; tested with comb structures. |
| CMP | Chemical-Mechanical Planarization | Polishing step that flattens each layer; source of centre, edge and ring signatures. |
| OPC | Optical Proximity Correction | Mask shape corrections; weak spots (hotspots) can fail per reticle shot. |
| EBR | Edge Bead Removal | Removes resist build-up at the wafer edge. |
| D0 | Defect density | Random defects per unit area; baseline yield Y ≈ e^(−D0·A). |
| HTOL | High-Temperature Operating Life | ≈ 1000 h biased at max temperature (AEC-Q100). |
| ELFR | Early Life Failure Rate | Short high-temperature operation of a large sample. |
| TC | Temperature Cycling | Package and interconnect fatigue test. |
| THB | Temperature-Humidity-Bias | 85 °C / 85% RH with bias. |
| HAST | Highly Accelerated Stress Test | 130 °C / 85% RH with bias. |
| RH | Relative Humidity | |
| HTSL | High-Temperature Storage Life | Unbiased bake. |
| HBM | Human-Body Model (ESD) | |
| CDM | Charged-Device Model (ESD) | |
| LU | Latch-Up | JESD78 test. |
| EM | Electromigration | Metal wear-out under current (wafer-level reliability). |
| TDDB | Time-Dependent Dielectric Breakdown | Gate-oxide wear-out. |
| HCI | Hot-Carrier Injection | Transistor degradation mechanism. |
| NBTI | Negative-Bias Temperature Instability | PMOS threshold drift. |
PCB, package & materials
| Abbr. | Stands for | Note |
|---|---|---|
| TCB | Thermo-Compression Bonding | Flip-chip attach with heat and force per die; fine pitch, low warpage. |
| MUF | Molded Underfill | Mold compound that also fills the gap under a flip-chip die. |
| CSAM | C-mode Scanning Acoustic Microscopy | Ultrasound imaging of voids and delamination inside packages. |
| AOI | Automated Optical Inspection | Camera inspection of RDL, bumps and balls in the assembly line. |
| KGD | Known-Good Die | Die that passed wafer sort and is released for assembly. |
| WLP | Wafer-Level Package | Package built on the whole wafer (fan-in) or a reconstituted wafer (fan-out). |
| PCB | Printed Circuit Board | |
| RDL | Redistribution Layer | Thin-film Cu wiring that routes die pads to balls (fan-out) or bumps. |
| UBM | Under-Bump Metallisation | Metal stack between die/RDL pad and the solder. |
| FOWLP | Fan-Out Wafer-Level Package | Die embedded in mold with RDL fanning out to balls; eWLB is one type. |
| CSP | Chip-Scale Package | Package only slightly larger than the die (FC-CSP = flip-chip CSP). |
| AiP | Antenna-in-Package | Antennas built into package layers. |
| IMC | Intermetallic Compound | Layer formed between solder and UBM/pad; grows with time and temperature. |
| CTE | Coefficient of Thermal Expansion | Mismatch between materials drives solder and bump fatigue. |
| MSL | Moisture Sensitivity Level | J-STD-020 rating: how long a package may sit out of dry pack before reflow. |
| ELK | Extreme Low-k dielectric | Fragile back-end dielectric in advanced nodes; cracks under bump stress. |
| NSMD | Non-Solder-Mask-Defined pad | PCB pad style that improves solder-joint fatigue life. |
| Dk | Dielectric constant | Sets line impedance and antenna tuning; shifts with moisture. |
| Df | Dissipation factor | Dielectric loss; key for RF loss at 77 GHz. |
| C-SAM | C-mode Scanning Acoustic Microscopy | Non-destructive imaging of delamination and voids. |
| PBO | Polybenzoxazole | Polymer dielectric used in RDL (like polyimide). |
| EOS | Electrical Overstress | Damage from overvoltage or overcurrent beyond ESD events. |
| BGA | Ball Grid Array | FC-BGA = flip-chip BGA. |
| eWLB | embedded Wafer-Level Ball-grid-array | Fan-out package with low RF loss. |
| AoP | Antenna-on-Package | |
| LoP | Launch-on-Package | RF launched from package into waveguide / antenna. |
| GCPW | Grounded Coplanar Waveguide | PCB transmission line at the ball launch. |
| SIW | Substrate-Integrated Waveguide | Waveguide formed with via fences in the PCB. |
| FR4 | Flame-Retardant epoxy-glass laminate | Standard low-cost PCB material. |
| ENEPIG | Electroless Nickel, Electroless Palladium, Immersion Gold | PCB surface finish. |
| ImAg | Immersion Silver | PCB surface finish. |
| HASL | Hot-Air Solder Leveling | Surface finish; too rough/uneven for 77 GHz. |
| PBT | Polybutylene terephthalate (PC = polycarbonate) | Radome plastics. |
| HFSS | High-Frequency Structure Simulator (Ansys) | 3D EM simulator (CST = Dassault's equivalent). |